Design Verification Engineer - Internal IP Job at Etched (San Jose)

Asic verification engineering intern

An exciting internship opportunity to make an immediate contribution to AMD's ne...

Location

Canada , Ottawa

Salary:

65000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

3rd/4th year Computer Engineering or Computer Science students
Understanding of digital design principles
Understanding of Object Oriented Coding practices
Experience with Systemverilog, C or C++ programming languages
Experience with Python, Perl or other scripting languages is an asset

Job Responsibility

Contribute to the development of advanced Systemverilog-UVM based verification environments and IP components
Write tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design
Learn to employ a Coverage-Driven Verification methodology with Constrained Random Stimulus
Review and contribute to verification plans and design specifications
Contribute to process improvements via automation of tasks and exploring and evaluating new tools and methodologies
Investigate and root cause issues found during the IP development stage

Fulltime

Senior Manager Silicon Design Engineer

AMD seeks a passionate, collaborative leader with strong technical skills and th...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

12-15 years full-time experience in IP hardware design
Proven experience managing and leading engineering teams
Proficiency in verilog/system verilog RTL logic design of high-speed, multi-clock digital designs
Verilog lint tools (Spyglass) and verilog simulation tools (VCS)
Clock domain crossing (CDC) tools
Detailed understanding of SoC design flows
Understanding of IP/SS/SoC Power Management techniques – Power Gating, Clock Gating
Outstanding interaction skills while communicating both written and verbally
Ability to work with multi-level functional teams across various geographies
Outstanding problem-solving and analytical skills

Job Responsibility

Lead a Silicon Engineering group and innovate with internal teams and external partners to create the next generation of computing technologies
Help bring to life cutting-edge designs, working closely with architecture, physical design, and product engineers to achieve first pass silicon success
Design of IP and subsystems with integration of AMD and other 3rd party IPs
Work collaboratively with other members of the IP team to support design verification, implementation, synthesis, constraints, static timing analysis, and delivery to SOC
Work in partnership with SOC teams to support the IP at SOC level, including connectivity, DFT, verification, physical design, firmware, and post-silicon bring-up

Senior Security Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Portugal , Moreira, Porto

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Knowledge about RTL design of hardware IP components
5+ years’ experience in RTL design or verification of hardware IP components
Knowledge of ASIC verification using System Verilog, UVM, or Verilog
Ability to create detailed specifications for test environments
MSc or PhD in Electrical Engineering or Computer Science
Strong understanding of IC Design flows and exceptional problem-solving and debugging skills
A strong communicator with excellent written and verbal skills
A team player who thrives in a collaborative international environment
An innovative thinker who is passionate about technology and continuous improvement
Detail-oriented and committed to delivering high-quality work

Job Responsibility

Designing and implementing RTL in Verilog and/or System Verilog for Security Applications
Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM
Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification
Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions
Working within an international team setup, contributing to global projects
Ensuring adherence to high-quality standards and best practices in digital design and verification processes

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

New

Design Verification Engineer - Interface IP

We are seeking a Design Verification Engineer to join our Interface IP DV team. ...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

5+ years of design verification experience
Experience digging deep into complex verification challenges and finding creative ways to expose corner-case bugs
Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches
Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
Thrive in a fast-paced startup environment and can take ownership of projects with minimal direction
Collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights

Job Responsibility

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

ASIC Digital Design, Sr Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Portugal , Moreira, Porto

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification
Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping with logical synthesis flows
Strong programming and scripting skills for test automation and data analytics (Python, C/C++, TCL)
Strong understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization techniques
Ability to interpret and apply digital architecture and SerDes standards documentation to develop robust verification solutions
Excellent technical documentation skills to ensure clear communication and knowledge transfer

Job Responsibility

Interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB
Evaluating and troubleshooting digital and mixed-signal circuits to ensure optimal performance and resolve complex design challenges
Collaborating with digital, firmware, and analog teams to solve verification challenges and improve design methodologies
Adapting and debugging internal verification environments to effectively replicate challenging scenarios
Identifying and implementing process improvements to enhance efficiency in design procedures and methodologies
Documenting verification environments, plans, and procedures to ensure clear communication and knowledge sharing across teams

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

ASIC Engineer, Formal Verification

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organ...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

New

2026 Summer Infinity Fabric Intern

As an Intern in the Data Fabric team, you will have the opportunity to work alon...

Location

Romania , Iasi

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Currently enrolled in a Romanian-based university Bachelor's or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science or related discipline
Knowledge/experience with programming and scripting languages such as C++ /System Verilog /TCL /Python /Perl /Shell
Exposure to Digital Circuit Design (VHDL / Verilog)
Knowledge of verification methodologies like UVM
Exposure to the digital systems and computer architecture
Familiar with development and debugging in Linux /Unix environment
Good written and verbal English

Job Responsibility

Contribute to the design and pre‑silicon verification of microprocessor IP and components
Develop, execute, and document verification test plans
Build and debug SystemVerilog testbenches (stimulus, monitors, checkers)
Analyze simulation results and debug RTL and testbench issues
Collaborate closely with design, verification, and architecture teams
Enhance verification and development flows using scripting and automation
Gain exposure to the full integrated circuit design lifecycle

Fulltime

ASIC Verification - Team Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Santa Clara

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience working with large verification projects, including cluster/subsystem and fullchip environments
Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion
Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements
Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
Comfortable and experienced with AI based tools to accelerate productivity

Job Responsibility

Pre-Silicon Verification
Improves verification efficiency through new and updated methodologies or tools
Defines verification strategies and test plans
Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels
Drives the development of verification environments, runs, and debugs simulations to drive quality
Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals
Performance
Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs
Determines type of performance model needed and appropriate model fidelity

Fulltime

Design Verification Engineer - Internal IP

Etched

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 18, 2026

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