Design Verification Engineer - Internal IP Job at Etched (San Jose)

Design Verification Engineer - Interface IP

We are seeking a Design Verification Engineer to join our Interface IP DV team. ...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

5+ years of design verification experience
Experience digging deep into complex verification challenges and finding creative ways to expose corner-case bugs
Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches
Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
Thrive in a fast-paced startup environment and can take ownership of projects with minimal direction
Collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights

Job Responsibility

End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
Understand vendor IP configurations and handle handshake with internal IP team
Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications
Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

IP Validation Design Engineer

At AMD, our mission is to build great products that accelerate next-generation c...

Location

Canada , Vancouver

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Experience in digital logic design/verification/post-silicon validation
Extensive experience with ASIC debug techniques and methodologies
Strong scripting skills (eg. Ruby, Python)
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
Must have excellent written and verbal communication skills
Must excel in a dynamic team working environment
Must be a self-starter and be able to independently drive tasks to completion
Bachelor’s or master’s degree majoring in EE, CS or related field

Job Responsibility

Drive the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s
Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features
Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
Developing knowledge of system architecture/debug and other internal IP’s
Supporting issues on customer platforms as requested by customer support teams

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Staff Digital Design Engineer

As a Staff level Design Engineer you will focus on the research, development and...

Location

United Kingdom , Penicuik

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in HDL, design capture and metadata languages (VHDL, System Verilog, C/C++, Python, TCL)
Proficient in Digital Signal processing and Linear Algebra
Expert in digital design techniques, especially for high speed
Experience in digital design, Digital Signal Processing, Linear Algebra
Experience in GIT, Perforce, Unix, LSF
Familiarity with scripting languages such as Python, Perl, Tcl
Bachelors, Masters or PhD in Computer Engineering, Computer Science or Electrical and Electronic Engineering

Job Responsibility

Research, design, development and productization of DSP and linear algebra IP solutions which target AMD FPGA programmable logic and AMD AIE array processors
Verification and validation of these designs
Collaboration with peer teams
Collaboration for continuous improvement of internal processes and techniques

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
Develop and implement methodologies and strategies to improve physical design efficiency and performance
Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
Implementation of functional ECO with least physical design impact
Design and implement the global clocking scheme at SOC and sub chip levels
Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers

Fulltime

Infinity Fabric Verification Engineer

The Infinity Fabric network on the chip verification team is growing and looking...

Location

United States , Santa Clara

Salary:

166400.00 - 249600.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Proven experience verifying complex design blocks at the IP or SoC level using SystemVerilog/UVM or related technologies
Comfortable creating and executing on testplans in collaboration with design and verification colleagues in a metric-focused environment
Architected and developed complex verification environments in SystemVerilog or C++ and infrastructure, including scripting using Perl, Ruby, Make, or the likes
Experience in developing or refactoring testbench, UVC, or BFM code using Object-Oriented Programming (OOP) principles
Exposure to RTL design, software development, formal verification, or other related domains
7-12 years industry experience is preferred
BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Job Responsibility

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects
Develop and enhance BFM/UVC for industry-wide and AMD internal protocols
Collaborate with architects, hardware engineers and multiple IP development groups
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture
Mentor junior engineers

Fulltime

Infinity Fabric Verification Engineer

The Infinity Fabric network on the chip verification team is growing and looking...

Location

United States , Austin

Salary:

144800.00 - 217200.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Architected and developed complex verification environments in SystemVerilog or C++ and infrastructure, including scripting using Perl, Ruby, Make, or the likes
Experience in developing or refactoring testbench, UVC, or BFM code using Object-Oriented Programming (OOP) principles
Exposure to RTL design, software development, formal verification, or other related domains
7-12 years industry experience is preferred
BS or MS degree in Electrical Engineering, Computer Engineering, or Computer Science

Job Responsibility

Develop and enhance SystemVerilog / UVM-based testbenches to verify new features for client, server, graphics, and semi-custom interconnects
Develop and enhance BFM/UVC for industry-wide and AMD internal protocols
Collaborate with architects, hardware engineers and multiple IP development groups
Interact with architects, RTL designers, performance engineers, and post-silicon validation engineers to develop deep expertise in the Infinity Fabric architecture
Mentor junior engineers

Fulltime

Senior Analog Design Engineer

For our customer, a leading global provider of microcontrollers and semiconducto...

Location

Turkey , Istanbul

Salary:

Not provided

sHR Consultancy

Expiration Date

Until further notice

Requirements

Typically 5 – 10 years of experience
Strong competence with various tools and procedures, reaching specialist level
Ability to work with minimal instruction – either independently or collaboratively
Ability to make good judgment in selecting methods/techniques for obtaining solutions
Able to confidently share own expertise and work to others
Able to make significant contribution to projects, programs and business initiatives with creativity and ingenuity
Ability to support and mentor less experienced team members
Cross cultural awareness and sensitivity
Results-oriented and able to deliver on-time under tight schedule
Ability to work both independently and part of a team

Job Responsibility

Design, verification, and simulation of CMOS Analog blocks for power management circuits including voltage references, bias circuits, comparators and amplifiers meeting performance, area and power specifications
Collaborate with block leads to achieve system and design strategy for power management products
Guide layout team to ensure quality of layout of own design
Drive silicon debugging and design characterization
Drive lab evaluation in collaboration with Application Engineers for own design
Produce high-quality documentation for own IP blocks
Working closely with DFT engineers to ensure that own blocks follow existing strategy and implementation for DFT
Work closely with test and product engineers to support test development and ramp to production
Coach and mentor less experienced team members
Contribute to schematic and layout block-level reviews for blocks initially designed by others

What we offer

A competitive salary and benefits package
USD based compensation model
Educational and development opportunities
Hybrid working option

Fulltime

Senior Security Design Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Portugal , Moreira, Porto

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Knowledge about RTL design of hardware IP components
5+ years’ experience in RTL design or verification of hardware IP components
Knowledge of ASIC verification using System Verilog, UVM, or Verilog
Ability to create detailed specifications for test environments
MSc or PhD in Electrical Engineering or Computer Science
Strong understanding of IC Design flows and exceptional problem-solving and debugging skills
A strong communicator with excellent written and verbal skills
A team player who thrives in a collaborative international environment
An innovative thinker who is passionate about technology and continuous improvement
Detail-oriented and committed to delivering high-quality work

Job Responsibility

Designing and implementing RTL in Verilog and/or System Verilog for Security Applications
Creating and designing test environments for digital hardware Security IP cores and subsystems using System Verilog and UVM
Conducting hardware verification of IP cores and subsystems utilizing modern verification techniques such as UVM or formal verification
Collaborating with hardware and software security experts to perform functional and performance analysis of embedded hardware/software IP solutions
Working within an international team setup, contributing to global projects
Ensuring adherence to high-quality standards and best practices in digital design and verification processes

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Select Country

Design Verification Engineer - Internal IP

Job Description

Job Responsibility

Requirements

Nice to have

What we offer

Looking for more opportunities?