CrawlJobs Logo

Design Verification Engineer - Interface IP

etched.com Logo

Etched

Location Icon

Location:
United States , San Jose

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

150000.00 - 275000.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Job Responsibility:

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
  • Understand vendor IP configurations and handle handshake with internal IP team
  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications
  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture
  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios

Requirements:

  • 5+ years of design verification experience
  • Experience digging deep into complex verification challenges and finding creative ways to expose corner-case bugs
  • Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches
  • Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
  • Thrive in a fast-paced startup environment and can take ownership of projects with minimal direction
  • Collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights

Nice to have:

  • Experience handling vendors and integration of IP/VIP’s
  • UVM/System Verilog
What we offer:
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Icon
Etched - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon
PREMIUM
More languages and countries
+ Unlock 31694 hidden job offers
Languages
English Čeština Deutsch Ελληνικά Español Français +15
Countries
United States United Kingdom India Canada Australia +
See plans
Plans from $2.99 / month

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Design Verification Engineer - Interface IP

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
  • 8+ years of experience in ASIC development, with a proven track record of leading complex project
  • Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
  • Strong digital design development and execution skills , solving bugs
  • Experience in grooming team of 1-4 engineers, interacting with many team
  • Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
  • Hands-on experience with industry-standard EDA tools and design flows
  • Deep knowledge on PCIe, axi , DMA, AHB interfaces
  • Expertise in high-performance and low-power design techniques
  • Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly
Job Responsibility
Job Responsibility
  • Design and implements IPs and subsystems
  • Dealing the best of class IPs for all SanDisk products
  • Fulltime
Read More
Arrow Right

Senior Design Verification Engineer

We are looking for a Senior Design Verification Engineer to join Microsoft's Sil...
Location
Location
United States , Raleigh
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
Job Responsibility
Job Responsibility
  • Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components
  • Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness
  • Develop Verification IP (VIP) components to verify home grown designs
  • Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments
  • Define and implement functional coverage and drive coverage closure
  • Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive
  • Develop scripts for verification and validation infrastructure
  • Fulltime
Read More
Arrow Right

Senior Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This role will require access to information that is controlled for export under export control regulations
  • 3+ years of experience working on Computer Architecture and SoC design and verification principles, including using industry standard HDLs like System Verilog
  • 3+ years of experience developing and using verification environments in industry standard languages like SVTB UVM or formal verification
  • 3+ years of experience in design verification with a proven track record of delivering complex SOC, SS or IP testbenches
  • Experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems
  • Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in Universal Verification Methodology (UVM) and C++
Job Responsibility
Job Responsibility
  • Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for SS- or SOC-level verification
  • Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness
  • Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments
  • Define and implement functional coverage and drive coverage closure
  • Run tests, debug failures to root cause, and recommend fixes
  • Apply your growth mindset to learn and adapt in a complex and dynamic environment
  • Collaborate across verification teams on vertical and horizontal reuse of components
  • Mentor and coach team members
  • Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers
  • Embody our culture and values
  • Fulltime
Read More
Arrow Right

Senior SerDes Verification Engineer

AMD is seeking a talented SerDes Verification Engineer to work on verifying and ...
Location
Location
Singapore , Singapore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience in SerDes verification or high-speed communication verification
  • Strong hands-on experience with verification methodologies such as UVM, SystemVerilog, or other simulation-based verification tools
  • Knowledge of high-speed serial protocols such as UCIe, PCIe, Ethernet, USB, DDR, or custom protocols
  • Experience in analyzing and interpreting signal integrity issues, jitter, BER, and eye diagrams
  • Solid understanding of SerDes architectures, link training, and equalization
  • Strong debugging skills, with the ability to work across multiple domains (timing, protocol, performance)
  • Familiarity with hardware description languages (HDL) like VHDL or Verilog
  • Strong analytical, problem-solving, and communication skills
  • Experience with DDR protocol (e.g., DDR3, DDR4, DDR5) for memory interface verification
  • Understanding of UCIe protocol and its role in chiplet-to-chiplet communication
Job Responsibility
Job Responsibility
  • Verification of SerDes Designs: Develop and execute verification plans and testbenches for SerDes IPs (Intellectual Property) and subsystems to ensure they meet functional and performance requirements
  • Testbench Development: Design and implement verification testbenches using industry-standard verification methodologies (e.g., UVM, SystemVerilog, VHDL)
  • Simulation and Debugging: Perform simulations, analyze results, and debug issues related to timing, protocol errors, and other design anomalies in SerDes blocks
  • Performance Evaluation: Evaluate and validate performance characteristics of SerDes systems including jitter, bit error rates (BER), signal integrity, eye diagrams, and other key metrics
  • Protocol Compliance Testing: Verify adherence to relevant SerDes protocols such as UCIe, PCIe, Ethernet, USB, DDR, DisplayPort, or custom protocols
  • Automated Testing: Develop automated regression tests to ensure the robustness and stability of the SerDes design over multiple versions and iterations
  • Collaboration: Work closely with the design, hardware, and software teams to troubleshoot issues, implement fixes, and verify design changes
  • Documentation: Create detailed reports and documentation on verification results, test scenarios, and issues found during testing
  • Continuous Improvement: Provide feedback for design and verification process improvements and contribute to innovation in verification strategies and methodologies
  • Fulltime
Read More
Arrow Right

Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
100600.00 - 199000.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • This role will require access to information that is controlled for export under export control regulations
  • As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
  • To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport
Job Responsibility
Job Responsibility
  • Establish yourself as an integral member of a pre-silicon verification and post-silicon validation team for the development of custom silicon components
  • Work with a team to write constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness
  • Develop Verification IP (VIP) components to verify home grown designs
  • Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments
  • Define and implement functional coverage and drive coverage closure
  • Collaborate with Architecture, Design, Firmware/Software, Product Engineering, Program Management and third-party vendor teams to ensure pre-and-post-Si testing is comprehensive
  • Develop scripts for verification and validation infrastructure
  • Fulltime
Read More
Arrow Right

Principal Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Raleigh
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
  • Provide proof of citizenship or US residency/protected status for export control assessment
  • 5+ years of pre-silicon subsystem or IP verification experience
  • Demonstrated expertise in leading verification of designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols
  • Demonstrated expertise in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges
  • Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff
Job Responsibility
Job Responsibility
  • Own or lead verification of complex flows at Fabric Interconnect or at block level
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop UVM-based verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion
  • Fulltime
Read More
Arrow Right

Senior Analog Design Engineer

The Interface & Custom Circuit Engineering team in AI-Silicon Engineering is see...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BSEE or equivalent, MSEE/PhD preferred
  • 7+ years of experience in analog circuit design, through full cycle post BSEE or equivalent
  • Experience with high-speed analog front-end serdes or D2D design (preferably PCIe, UCIe, D-PHY, USB), data-converters, PLLs, Regulators and all associated blocks in analog designs from architecture till silicon validation support
  • Experience in Design partitioning, power/jitter budgeting and timing analysis
  • Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD/Aging & Signal Integrity Design
  • Experience with the use of CAD-tools (Cadence, Mentor, Synopsys) for circuit schematic entry, simulations, post layout extractions, Mixed-mode simulations
  • Delivered Analog IP’s successfully in mass production in FinFET processes
  • Experience in mentoring individual engineers
  • Working with multiple stakeholders (arch/design/layout/silicon validation/project managers) to execute full design cycle till silicon
  • Excellent communication skills and self-motivated that can collaborate with larger teams within Microsoft
Job Responsibility
Job Responsibility
  • Lead Analog designs and delivery of cutting edge, high-performance, high-speed, low-power Analog IP designs for interconnectivity solutions and fundamental Analog circuit blocks for various Microsoft products in various process nodes including deep FinFet, following industry best practices
  • Technically deliver complex blocks that will produce schematics, verify in simulation, complete timing/jitter/power budgets and work with mask layout teams to deliver a final IP GDS
  • Coordinate tasks with junior members of the team, develop plans for Analog IP execution, follow processes/methodologies to deliver IP blocks
  • Coordinate bench validation of IP in Silicon, and IP characterization on bench and tester
  • Use established flows/methodologies/processes for execution
  • Work along with other members of the team to deliver IP’s, including project planning, schedule tracking, report generation
  • Interface with RTL, Verification and P&R team
  • Fulltime
Read More
Arrow Right

Fpga design verification engineer

Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Lead verification efforts for FPGA IP and subsystems within high-performance wireless communication systems
  • Develop and execute comprehensive verification plans ensuring functional correctness and robustness of FPGA designs
  • Design and maintain SystemVerilog/UVM-based test environments for complex digital systems
  • Create constrained-random test cases, assertions, and scoreboards to validate design behavior
  • Execute simulations and debug issues using industry-standard tools (e.g., VCS or equivalent)
  • Analyze and close functional and code coverage gaps to ensure complete verification sign-off
  • Perform root-cause analysis of RTL and system-level defects independently
  • Collaborate with design and system teams to review specifications, interfaces, and edge cases
  • Contribute to architecture and design reviews as a verification subject matter expert
  • Drive adoption of AI-assisted verification techniques to improve efficiency and coverage
Read More
Arrow Right