Design Verification Engineer - Azure DPU Silicon

• Define and execute block and subsystem-level verification strategy for DPU IPs
• Develop SystemVerilog UVM testbenches, environments, and reusable components
• Create constrained-random and directed tests, assertions, and functional coverage
• Collaborate closely with architecture, RTL design, and post-silicon validation teams
• Drive improvements in verification methodology, automation, and debug efficiency
• Contribute to system-level validation and co-simulation with software and firmware teams

• 5+ years of experience in ASIC/SoC design verification
• Strong proficiency in System Verilog and UVM methodology
• Solid understanding of computer architecture, networking, or memory subsystems
• Experience with high-speed I/O (PCIe, Ethernet) or NIC/acceleration pipelines preferred
• Ability to work in a collaborative, cross-functional environment with strong technical ownership

Experience with high-speed I/O (PCIe, Ethernet) or NIC/acceleration pipelines