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Design For Test Engineer

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AMD

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Location:
United Kingdom , Cambridge

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

We are seeking a experienced Design For Test engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and experience in DFT methodologies, particularly in the context of CPU core design and development. As a DFT engineer in AMD's CPU Cores team, you will have an outstanding opportunity to work on AMD’s next-generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology. As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success.

Job Responsibility:

  • Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products
  • Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort
  • Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs
  • Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration
  • Work closely with DFT Tool Vendors and drive improvements based on the testability requirements
  • Develop efficient DFx flows and methodology compatible with front end and back end design flows
  • Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement
  • Mentor and coach junior engineers

Requirements:

  • Strong experience in Scan based testing and industry standard ATPG CAD tools
  • Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
  • Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools
  • Experience in MBIST implementation and verification
  • Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
  • Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills
  • Good understanding of STA concepts
  • Experience in Spyglass based DFT DRC checks at RTL level
  • Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc
  • Prior experience in working with Version control systems like perforce, git etc
  • Prior work experience in high-performance and low-power designs
  • Understanding of low-power design flows such as power/clock gating, multi-Vt and voltage/frequency scaling etc
  • Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks
  • Familiarity with System Verilog and UVM
  • Exposure to post-silicon testing and tester pattern debug
  • Strong problem solving and debug skills across various levels of design hierarchies
  • Must have good communication skills and the ability to work in a worldwide team environment
  • Exposure to leadership or mentorship
  • Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering

Nice to have:

  • Experience in MBIST implementation and verification will be a strong plus
  • Good understanding of STA concepts having handled DFT timing closure before would be a plus
  • Experience in Spyglass based DFT DRC checks at RTL level would be a plus
  • Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus
  • Prior work experience in high-performance and low-power designs would be a huge bonus
  • Understanding of low-power design flows such as power/clock gating, multi-Vt and voltage/frequency scaling etc will be a plus
  • Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus
  • Familiarity with System Verilog and UVM would be a plus
  • Exposure to post-silicon testing and tester pattern debug are major assets
  • Exposure to leadership or mentorship is an asset

Additional Information:

Job Posted:
March 04, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
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