CrawlJobs Logo

Design Engineer – IPS

Germany, Munich · Job Posted January 02, 2026
Apply Position
Job Link Share

Job Responsibility

  • Responsibility for the quality of the cable concepts developed
  • Ensuring that the flexible cables developed meet all technical requirements and quality standards
  • Project responsibility
  • Responsibility for the progress and delivery of projects within the specified time frame
  • Technical advice and support
  • Supporting other departments or customers with technical expertise and advice in the field of flexible cables and the use of “IPS Cable Simulation”

Requirements

  • CATIA knowledge is a must
  • 2+ years in field
  • Development and design of flexible cables
  • Adoption of cable concepts from preliminary and concept development, as well as maintenance and further development through to series production of flexible components
  • Maintenance of IPS installation spaces for the assigned product lines
  • Use of “IPS Cable Simulation”
  • Use of the IPS Cable Simulation tool for the design, construction, and simulation of flexible components
  • Ensuring that all cable concepts function in simulation in compliance with the latest vehicle kinematics/tulle database and installation space environment, taking into account the minimum requirements
  • Simulation using IPS Cable Simulation
  • Performing simulations to check dynamic cable concepts for the developed cables
  • Documentation and reporting
  • Creating and maintaining final documentation to document approval in VOOFit for the developed cable concept (approvals are not permitted without final documentation “Verf / Vorf / Prof / change approvals”)
  • Communication of results and progress to the development team or project management
  • Collaboration with other departments
  • Close collaboration with other development teams in the areas of VDC / RDS / BVA / BS / Halter
  • Optimization of existing cable concepts
  • Analysis and continuous improvement of existing solutions based on feedback and new findings

What we offer

  • Attractive salary (negotiable based on technical knowledge)
  • Meal Tickets
  • One bonus vacation day for every 2 years of seniority in our company
  • Flexible working time
  • Private medical insurance package
  • Bonus for internal recommendation
  • Access to over 650 sports centers in the 7Card network
  • Opportunity to read a lot of books from Bookster
  • Environment provided for professional development
  • High tech infrastructure

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Similar Jobs for

Design Engineer – IPS

8 matching positions

Senior Staff Silicon Design Engineer (Design Verification)

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong experience in ASIC/SoC design
  • Strong hands-on verilog development experience, familiar with scripting languages like Perl
  • Good experience on complicate hub,control IP design
  • Strong problem solving, independent thinking, teamwork and communication skills
  • Bachelor or Master degree in E&E or Computer Engineering. (Preferred Master Degree)
Job Responsibility
Job Responsibility
  • Own part of IP feature design with cooperation with other designers
  • As one of IP design team members, own for IP level design work, including architecture define (partly own or join), spec documentation, RTL coding, RTL delivery and signoff
  • The target IP is used for all AMD mainstream products, product generation upgrade, reusability and scalibility need to be considered in architecture define and RTL maintain, as well as compliant to system application and sw/fw/hw cooperation.
  • Need to co-work with other teams closely, include communication with AMD global soc architect and IP architect, closely work with verification team, trace and support backend work, silicon validation support.
What we offer
What we offer
  • AMD benefits at a glance.
Read More
Arrow Right
New

Fpga Developer / Fpga Design Engineer (4g/5g Radio – Datapath / Ru Fpga Design)

Location
Location
Canada , Ottawa
Salary
Salary:
Not provided
myticas.com Logo
Myticas Consulting
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Hands-on DSP (Digital Signal Processing) expertise including FFT, Beamforming, and Digital Filter implementation
  • Strong MATLAB / Simulink experience
  • SystemVerilog and RTL design experience for complex FPGA-based systems
  • Experience developing FPGA IP and architectures for 4G/5G Radio Units
  • Knowledge of AXI and Ethernet protocols
  • Experience with FPGA development tools including Altera Quartus and MATLAB/Simulink
  • Exposure to model-based design methodologies and FPGA implementation workflows
  • Understanding of wireless communications, 4G/5G radio architecture, O-RAN, LTE, eCPRI, CPRI, and PTP protocols is desirable but not mandatory
  • Experience optimizing FPGA resource utilization, timing closure, and high-performance datapath processing
  • Knowledge of high-speed interfaces such as Ethernet, PCIe, JESD204B/C, AXI, and SERDES technologies
Read More
Arrow Right

Systems Design Engineer - RAS Enablement

We are looking for a dynamic, energetic and a strong Enablement Engineer for RAS...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years of silicon validation for multiple any SoCs especially x86 containing multi core CPU/GPU subsystems with focus on RAS implementation across different IPs
  • Expertise of RAS features pertaining to Memory, PCIE, Reset flows, Out of Band features
  • Strong understanding of x86 HW, FW and BIOS Architecture
  • Strong communication and cross-functional collaboration abilities
  • Exposure to certain stages of Silicon Validation will be crucial, including use-case validation
Job Responsibility
Job Responsibility
  • Owning RAS sub system implementation based on the Product requirements
  • Conducting day-to-day experiments for RAS
  • Maintaining Test plans and reports and scrubbing the JIRA tickets on a periodic basis
  • Developing required test scripts for small tasks
  • Problem solving
  • Work with the RAS Lead and senior members in refining the processes, and demonstrate keen interest to learn and explore new methods/ideas pertaining to memory subsystem
  • Fulltime
Read More
Arrow Right
New

Fullchip Floorplan Design Engineer

As part of AMD's S3 (Semi-Custom) organization, you will work within the Physica...
Location
Location
Canada , Markham
Salary
Salary:
155200.00 - 232800.00 CAD / Year
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience in SoC physical design with successful tapeouts
  • Strong ownership of full-chip floorplanning (partitioning, macro placement, integration)
  • Solid understanding of physical design flows and impact on timing, power, and implementation
  • Hands-on experience with Fusion Compiler or similar tools (e.g., Innovus)
  • Experience with feedthrough planning, bus topology, and timing-aware floorplanning
  • Understanding of SoC architecture (e.g., AXI, source-synchronous interfaces, test)
  • Proven collaboration with RTL, IP, DFT/DFX teams
  • Scripting skills (Tcl, Perl, Python, or Shell) for automation
  • Experience with large-scale SoC designs and low-power considerations
  • Experience improving design productivity through automation or advanced methods
Job Responsibility
Job Responsibility
  • Own full-chip floorplanning (partitioning, macro placement, integration)
  • Translate RTL → full-chip floorplan (chip structure, block definition)
  • Plan pins, feedthroughs, and bus topology (incl. source-synchronous interfaces)
  • Define repeater strategy for timing and signal integrity
  • Optimize floorplan for timing, power, and area (PPA)
  • Run feasibility / tradeoff analysis for floorplanning decisions
  • Collaborate with RTL, architecture, DFT/DFX, and PD teams
  • Use tools like Fusion Compiler / Innovus for implementation
  • Build automation (Tcl / Perl / Python) to improve execution
What we offer
What we offer
  • Benefits offered are described: AMD benefits at a glance
  • Fulltime
Read More
Arrow Right
New

Staff Silicon Design Engineer - Emulation

A successful candidate will work with senior design and design verificaiton team...
Location
Location
Serbia , Belgrade
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Experience in system and subsystem level designs
  • Experience with FPGA flows, synthesis and PnR
  • Experience in RTL design, verification, and embedded FW
  • Excellent programing skills in C/C++, SystemVerilog
  • Experience working with Verilog/SystemVerilog based designs
  • Experience with UVM based testbenches
  • Strong debugging and problem-solving skills
  • Debugging experience with waveform analyzers
  • Scripting/preprocessing
  • Experience working in emulation and prototyping
Job Responsibility
Job Responsibility
  • Execute emulation test plans, ensuring high-quality outcomes and adherence to timelines
  • Collaborate effectively with team members across North America to align on project goals, share insights, and implement best practices
  • Contribute in the design and implementation of emulation test benches
  • Contribute into continuously improving the emulation methodology
  • Experience implementing synthesizable models using SystemVerilog
  • Drive debug with designers and verifiers
  • Collaborate with IP design and verification teams on test planning and task execution
  • Work on various emulation methodologies such as: Transactors, Simulation Acceleration, Hybrid VMs
  • Execute verification of the latest features and protocols
  • Integrate, bring-up and debug standard interfaces like UART, JTAG, I2C, USB
  • Fulltime
Read More
Arrow Right
New

Mts Silicon Design Engineer

The focus of this role is to plan, build, and execute the verification of new an...
Location
Location
India , Karnataka
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Experienced with Verilog, System Verilog, C, and C++
  • Graphics pipeline knowledge
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
  • Strong background in the C++ language, preferably on Linux with exposure to Windows platform
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
Job Responsibility
Job Responsibility
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Read More
Arrow Right
New

Senior Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
Malaysia , Gelugor
Salary
Salary:
Not provided
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS/MS in Electrical or Computer Engineering
  • 8+ years of experience
  • Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, Innovus etc.
  • Strong understanding of constraints generation, STA, timing optimization, and timing closure.
  • Great communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams.
  • Proven track record of implementing designs through synthesis, floorplanning, place and route, extraction, timing, and physical verification.
Job Responsibility
Job Responsibility
  • Own and drive floorplanning and design planning for optimizing Mixed-Signal IPs with Analog and Digital components
  • Own and drive execution from synthesis to place and route of IPs, all signoff including timing signoff, physical verification, EMIR signoff , Formal Equivalence, and Low Power Verification.
  • Define Analog / Digital interfaces to facilitate design convergence and optimize power delivery for optimal performance (topmetal & bump planning)
  • Have close collaboration with RTL team to help drive and resolve design issues related to toplevel and block closure.
  • Influence tools, flows, and overall design methodology in design construction, signoff, and optimization with a data driven approach.
  • Make good independent technical trade-offs between power, area, and timing.
  • Provide technical leadership and collaborate across teams to come up with the best solution possible with a One Microsoft mindset.
  • Fulltime
Read More
Arrow Right

Silicon Design Engineer

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proficient in IP level ASIC verification
  • Proficient in debugging firmware and RTL code using simulation tools
  • Proficient in using UVM testbenches and working in Linux and Windows environments
  • Strong background with UVM, Verilog, System Verilog, C, and C++
  • Developing UVM based verification frameworks and testbenches, processes and flows
  • Automating workflows in a distributed compute environment
  • Good understanding and hands-on experience in the UVM concepts and SystemVerilog language (SVA, UVM scoreboard)
  • Good working knowledge of SystemC and TLM with some related experience
  • Over 7 yrs of digital IP verification with SV/UVM/formal verification or new methodology of the industry
  • Bachelors or Masters degree in computer engineering/Electrical Engineering
Job Responsibility
Job Responsibility
  • Candidate should be able to work independently on various DV task and providing technical guidance to DV team
  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL and firmware engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
  • Fulltime
Read More
Arrow Right