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DDR Lead Verification Engineer

India, Bangalore Employment contract · Job Posted June 16, 2026
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Job Description

The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s Memory Controller IP, resulting in no bugs in the final design.

Job Responsibility

  • Collaborate with architects, hardware engineers to understand the new features to be verified
  • Build test plan documentation, accounting for interactions with other features
  • Estimate the time required to write the new feature tests and any required changes to the test environment
  • Build the directed and random verification tests
  • Debug test failures to determine the root cause
  • work with RTL engineers to resolve design defects and correct any test issues
  • Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Requirements

  • Proficient in IP level ASIC verification
  • Proficient in debugging RTL code using simulation tools
  • Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage
  • ASIC design verification experience with 7+Years
  • Hands on experience in developing complex UVC
  • Good debugging skill and good knowledge of verification tool and methodology
  • Hands on experience with coverage planning, coding, and coverage closure
  • Should have worked on developing testplan at module level/IP level /Chip-level project
  • Mentoring Juniors and ensuring that the team achieves technical goals with high quality
  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

  • Scripting language experience: Perl, Ruby, Makefile, shell preferred
  • Exposure to leadership or mentorship is an asset
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