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AMD Logo AMD · IT - Software Development

Datacenter Power and Performance Modeling Engineer

United States, Santa Clara Employment contract 166400.00 - 249600.00 USD / Year · Job Posted May 17, 2026
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Job Description

AMD's Datacenter Performance Group is seeking talented, motivated engineers to drive the Power Constrained Performance of our industry-leading AI/ML/HPC GPUs. The role will involve many aspects of Perf@Power attainment, including pre-Si power modeling, post-Si correlation, workload analysis, setting PPA targets and driving attainment, power/perf roll-ups and reporting, methodology innovations and development. Being passionate about performance and power efficiency is a key ingredient for success in this role.

Job Responsibility

  • Pre-silicon power modeling (HW-IP, SoC, Multi-GPU nodes/clusters), Power-constrained Performance projections and Reporting
  • Support Pre-silicon PPA target setting (for HW IPs, FW and SW)
  • Support PPA attainment by working with various engineering functions including SOC architecture, System Design, IP Design, Foundry team, Physical Design, Software, Power Management, Post-si validation
  • Post Si calibration of models and Power/Performance debug
  • Analyzing key workloads for power behaviors and optimization opportunities
  • Scripting and coding to automate routine tasks, building new tools for wider usage

Requirements

  • Background in Computer Architecture, Power and Performance
  • Experience in Soc Level Power/Performance projections, modeling and optimization
  • Experience in power modeling for digital and analog IPs
  • Familiarity with digital logic physical design and power management techniques (clock gating, power gating, V-F curves, p-states, on-die voltage regulation, clock integrity, etc..)
  • Experience in post-silicon power/performance debug, model correlation
  • Fluency in Excel based data analysis & charting, scripting experience in Ruby, Python

Nice to have

  • Verilog RTL coding experience/understanding is desirable, especially low power design techniques
  • Knowledge of DL/ML/LLM workloads will be a bonus
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