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The person will be part of AMD's CPU Performance Validation team. This team is part of AMD's global CPU Performance teams and plays a critical role in next generation AMD CPU design. Involves having deep understanding of existing AMD X86 CPU architecture and microarchitecture ranging from CPU pipeline stages to various complex features and structures, debugging performance issues of RTL, giving feedback to design team for latest gen CPU in pre-silicon and emulation environment. We are seeking a highly skilled Verification Engineer who can carry out cutting-edge unit-level verification for complex CPU designs. You will own the creation of comprehensive test plans, drive coverage closure, and collaborate closely with RTL designers to resolve issues and achieve tape-out readiness. Beyond simulation, you will support emulation and post-silicon validation efforts, while setting best practices and mentoring junior engineers to elevate the team’s verification capabilities.
Job Responsibility:
Architect and implement unit-level verification environments using C++/SystemVerilog/UVM
Develop detailed test plans for functional and performance verification of Load/Store, Scheduler, and Execute Units
Create directed and random stimulus, checkers, and coverage models
Debug simulation failures and collaborate with RTL designers to resolve issues
Drive coverage closure and ensure high-quality tape-out readiness
Support emulation and post-silicon validation efforts
Mentor junior engineers and contribute to verification best practices
Requirements:
Strong understanding of out-of-order execution, memory ordering, and cache coherence
Proficiency in SystemVerilog, UVM, C++, Python
Experience with x86, ARM, or RISC-V architectures
Familiarity with simulation tools (VCS, Verilator), waveform debugging, and scripting
Excellent problem-solving and communication skills
Excellent inter-personal, communication skills and ability to work in a fast-paced exciting environment
Should be a self-learner and always ready to upgrade his/her skills
Experienced verification engineer with deep expertise in high-performance CPU verification
Proven track record in developing scalable verification environments, driving coverage closure, and collaborating across architecture, RTL, and post-silicon teams