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WHAT YOU DO AT AMD CHANGES EVERYTHING. At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
Job Responsibility
Act as the technical lead for CPU power estimation and optimization, shaping power strategy for high-performance CPU cores
Deliver credible power projections from early architecture through sign-off and influence CPU design decisions across multiple generations
Define CPU power architecture including core, cache (L1/L2/L3)
Establish voltage domains power goals for each states, performance states, low-power modes, and CPU use-case power envelopes
Drive power-performance-area (PPA) tradeoffs for different goals for CPU units
Quantify power cost of CPU micro-architectural features (pipeline depth, width, speculation, cache structures, predictors, queues, buffers)
Evaluate power impact of ISA extensions, frequency targets, and workload characteristics
Use prior-generation CPU data to guide next-generation architectural decisions
Own early CPU power estimation using architecture-level parameters (flops, SRAM bits, activity proxies, frequency, topology)
Define correlation strategy from early estimates to RTL power to physical implementation to silicon
Ensure estimates are actionable for CPU architecture and program planning decisions
Develop and maintain CPU-specific power models at core and CCX
Drive scalable estimation frameworks (analytical, statistical, or ML-assisted) suitable for early CPU planning
Standardize CPU power estimation methodologies across teams and programs
Partner with CPU Architects, RTL, Physical Design, CAD, and Platform teams to drive power-informed decisions
Serve as reviewer for CPU power assumptions and estimates used in exec and design reviews
Mentor senior engineers in CPU power modeling and estimation techniques
Identify architectural power-reduction opportunities across core and uncore
Influence CPU roadmap decisions with quantified power impact and risk assessment
Balance peak performance goals with sustainable power efficiency
Ensure CPU power models reflect realistic workloads (client, server, AI, mixed workloads)
Account for DVFS behavior, boosting, throttling, and residency in CPU power estimates
CPU power architecture definitions adopted across multiple programs
Trusted early power estimates that meaningfully predict late-stage and silicon power
Architectural tradeoff analyses that directly influence CPU design choices
Requirements
Deep expertise in CPU micro-architecture and power drivers
Strong background in power modeling, estimation, and correlation for high-performance CPUs
Proven ability to influence architecture decisions using quantitative power analysis
Advanced-node CPU design experience
Pre-silicon to post-silicon power correlation experience
Experience defining reusable CPU power methodologies adopted at scale