CPU Physical Design Lead Job at AMD (Bangalore)

Physical Design Lead - CPU Team

The position will involve working with a very experienced CPU physical design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

Lead Soc Physical Design Engineer

As a member of the Strategic Silicon Solution Group Full Chip Physical Design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Minimum 15+ years of relevant work experience
Expertise in ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
Expertise in Signoff tools like Primetime for Timing, Calibre for DRC/LVS, Ansys Redhawk on EMIR, PT-PX for Power signoff
Should have worked as a go to person or technical lead for at least few full chip projects
Strong technical leadership and ability to mentor/guide/coach design engineers
Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
Should have good scripting experience in Shell, Python, Perl, TCL, UNIX along with decode/debug old existing scripts
Bachelors or Master's degree in Computer/Electronics/Electrical Engineering
Experience in 5nm & below technologies
Hands-on in reference flows, excellent debugging skills

Job Responsibility

Full chip level Die size estimation, Floor-planning, Power planning, IO planning, package compatibility, IO ring creation and ESD analysis
Full chip Hierarchical planning, block planning , block level constraints, hierarchical clock tree implementation, block integration and chip finishing
Low power design with power estimation/optimization including clock gating, power gating, power switch implementation and other low power techniques to reduce total power consumption
Full chip/Sub-system/Partition level Synthesis, Logic equivalence, implementation of low power UPF/CPF
Full chip / sub-system level constraints, MMMC & cross talk aware timing closure with latest OCV based analysis
RTL2GDSII design implementation and flow debug top down or bottoms up at chip level
PPA (Power, Performance, Area and Schedule) closure and flow development for key IPs like CPU, Graphics, Multimedia, Fabric cores and/or other critical sub-systems
Low Power signoff like Static and Dynamic power analysis at top level and/or sub-system level
Full chip / sub system level Clock tree synthesis and advanced clock tree implementation
Top level ECO strategy for RTL, pre-physical and post-route implementation considering timing, congestion and logic equivalence

Physical Design Lead - CPU

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Rtl design lead - cpu team

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

6+ years of experience in Digital IP/ASIC design and Verilog RTL development
Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
Should possess expertise in front-end EDA tools sign-off and its flows
Familiarity with low power design and low power flow is an added plus
Ability to program with scripting languages such as Python or Perl is a plus
Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
Proven interpersonal skills, leadership and teamwork
Excellent writing skills in the English language, editing and organizational skills required

Job Responsibility

RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
Architect and design of power management features, cache, coherency
Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
Responsible for the inter IP integration issues resolution
Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
Architecting, micro-architecting and documentation of the design features
Lead design team from all aspects of the RTL deliverables
Mentor the junior members of the RTL team to meet the team goals
Represents AMD to the outside technical community, partners and vendors

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Field Application Engineer - Datacenter

We are looking for our next team member to support this strategic Mega Datacente...

Location

United States , Bellevue

Salary:

203760.00 - 305640.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Excellent interpersonal and communication skills (written, verbal and presentation) with a balance of hardware, system architecture and application software expertise
Proven track record in CPU and server system architecture, server benchmarks, GPU computing, FPGA accelerators, and server platform enablement
Excellent problem-solving, time-management, prioritization, and organizational skills, able to lead complex problems, involving multi-disciplined, multi-functional teams and many priorities at once
Ability to cultivate strong internal (sales, marketing, engineering) and external (customer) relationships
Physical requirement: able to lift up to 50 lbs. (racking hardware)
Willing to travel up to 25%
Proven experience as a senior level engineer (or equivalent technical role) balanced with experience in a customer-facing role
Proven experience in server platform architecture and/or platform development experience
Proven knowledge in any of these market verticals: cloud computing / benchmarking, high performance computing, networking, software defined storage and data analytics
Expertise in server software ecosystem in the one or more of these areas: Windows Server, Linux, hypervisors (Linux-KVM and Xen), NGINX, Redis, Apache Web Server, existing cloud offering such as AWS EC2, GCP and Microsoft Azure, and profiling / performance optimization tools

Job Responsibility

Articulate the benefits of AMD based technology offerings for the cloud service provider and MDC market verticals
Provide hands-on, expert-level technical guidance to systems engineers and application developers
Partner with other AMD subject matter authorities to tackle specific customer challenges
Lead technical design sessions
architect and detail technical solutions that are aligned with end-user objectives
Architect, install and test solutions in-house, as needed, to ensure successful deployments and evaluations
Design and lead the execution of evaluations to ensure a quality solution is delivered, providing technical assistance to sales for overall account strategy based on AMD datacenter solutions
Gather a solid understanding of the competitive landscape and clearly articulate the technical differentiation and value proposition associated with AMD versus our competitors
Drive customer feedback into AMD sales, business unit and engineering teams
Provide technical guidance to sales personnel and the customer in the evaluation, design and development of AMD based server and/or data center solutions as identified by sales leadership

Fulltime

New

Infrastructure and virtualization architect (data center)

We are seeking a highly skilled Infrastructure and virtualization engineer speci...

Location

Hungary , Budapest

Salary:

Not provided

Randstad

Expiration Date

May 31, 2026

Requirements

Deep Hypervisor Expertise: Expert-level knowledge of Hyper-V architecture (beyond simple VM creation). You must understand how hardware choices impact hypervisor performance and consolidation
Enterprise Server Architecture: Proven experience in designing virtualization-aware hardware layouts and maintaining standardized templates
Storage Platforms: Strong knowledge of Fiber Channel-based storage, including performance tiering, scalability tradeoffs, and cost-benefit analysis for long-term consolidation
Network Architecture: High-level understanding of multi-NIC layouts, awareness of management, backbone, customer traffic and their operational and security implications
Hands-on Mentality: Mandatory experience in live production environments. You must be comfortable moving from a design whiteboard to solving a high-priority ticket
Contractual Awareness: Experience working within the constraints of SLAs and customer-facing platforms
Technical Ownership: You are the person who steps up during outages and complex troubleshooting scenarios
Communication: Excellent English communication skills, with the ability to explain technical complexities to non-technical clients and stakeholders
Collaboration: Ability to work with external consultants without losing technical ownership of the internal environment

Job Responsibility

Lead the Data Center Move: Design the physical and logical migration paths, ensuring minimal downtime and architectural integrity during the transition
Architect & Standardize: Create and maintain standardized host templates (CPU density, memory ratios, NIC/HBA layouts) for both shared and dedicated environments
Capacity & Lifecycle Management: Lead capacity planning, consolidation strategies, and EOL (End-of-Life) planning to ensure platforms scale efficiently
Operational Execution: Act as the technical specialist within the Operations team. This includes picking up tickets, troubleshooting complex outages, and participating in the on-call rotation (one week every three weeks). Provides technical ownership and responsibility during outages and complex troubleshooting
Collaborative Design: Work alongside external consultants and project managers to validate designs and ensure hardware choices align with automation and patching goals

What we offer

International working environment
Opportunity to travel abroad
Competitive level of renumeration
Work with latest technologies
Flexible working condititons

Fulltime

CPU Physical Design Lead

AMD

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
February 13, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for CPU Physical Design Lead

Physical Design Lead - CPU Team

Lead Soc Physical Design Engineer

Physical Design Lead - CPU

Rtl design lead - cpu team

Senior RTL Design Lead

Senior Staff Physical Design Engineer

Field Application Engineer - Datacenter

Infrastructure and virtualization architect (data center)

CPU Physical Design Lead

AMD

Location:India , Bangalore

Category:IT - Software Development

Contract Type:Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:February 13, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for CPU Physical Design Lead

Physical Design Lead - CPU Team

Lead Soc Physical Design Engineer

Physical Design Lead - CPU

Rtl design lead - cpu team

Senior RTL Design Lead

Senior Staff Physical Design Engineer

Field Application Engineer - Datacenter

Infrastructure and virtualization architect (data center)

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Job Posted:
February 13, 2026