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Responsible for verifying latest gen complex Ryzen CPU clusters/blocks using formal methods. You'll engage on creation of formal proofs, abstraction models, and verification strategies to ensure correctness, collaborating closely with architects, RTL designers, and validation teams.
Job Responsibility:
Perform formal verification (model checking, equivalence checking) on CPU microarchitecture/IP blocks
Develop formal proofs, abstraction models, and convergence methodologies to maximize coverage and bug hunting
Lead ROI analysis to balance formal vs. dynamic methodologies
Work with architects, RTL designers, and verification teams to resolve failing assertions and improve design quality
Look for potential sign-off for critical blocks to guarantee exhaustive proof and reduce silicon escapes
Support post-silicon failure debug and sighting resolution when required
Maintain and enhance formal infrastructure (flows, abstraction techniques, tools)
Investigate new formal techniques and define reusable verification methodologies for the team
Requirements:
Bachelor’s, Master’s, or Ph.D. in Computer Engineering, Electrical/Electronic Engineering, Computer Science, or related field
5–10 years exp in formal verification for logic/microarchitecture IP— preferably CPU-related
Proven experience using formal engines (e.g. JasperGold, VC Formal) for bug hunting
Skilled in assertion languages (SystemVerilog Assertions) and HDL modeling (Verilog/VHDL/SV)
Strong scripting or programming ability (Python, Tcl, Perl)
Analytical mindset with intellectual curiosity
ability to uncover hidden verification gaps
Exceptional communicator and collaborator in cross-functional environments
Mentorship or technical ownership experience—leading reviews and guiding junior engineers
Nice to have:
Deep understanding of CPU microarchitecture topics (in-order/out-of-order execution, pipelines, memory consistency, coherence, ISA, security, floating-point, etc.)
Advanced degree (M.S. or Ph.D.) specializing in formal methods or microarchitecture
Experience with CPU post-silicon validation and debug
Familiarity with SoC verification flows, security IPs (e.g., secure enclaves), or system-level proof approaches