CPU Design Verification Architect Job at AMD (Bangalore)

Rtl design lead - cpu team

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

6+ years of experience in Digital IP/ASIC design and Verilog RTL development
Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
Should possess expertise in front-end EDA tools sign-off and its flows
Familiarity with low power design and low power flow is an added plus
Ability to program with scripting languages such as Python or Perl is a plus
Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
Proven interpersonal skills, leadership and teamwork
Excellent writing skills in the English language, editing and organizational skills required

Job Responsibility

RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
Architect and design of power management features, cache, coherency
Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
Responsible for the inter IP integration issues resolution
Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
Architecting, micro-architecting and documentation of the design features
Lead design team from all aspects of the RTL deliverables
Mentor the junior members of the RTL team to meet the team goals
Represents AMD to the outside technical community, partners and vendors

Design For Test Engineer

We are seeking a experienced Design For Test engineer to join our CPU Cores team...

Location

United Kingdom , Cambridge

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience in Scan based testing and industry standard ATPG CAD tools
Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools
Experience in MBIST implementation and verification
Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills
Good understanding of STA concepts
Experience in Spyglass based DFT DRC checks at RTL level
Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc
Prior experience in working with Version control systems like perforce, git etc

Job Responsibility

Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products
Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort
Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs
Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration
Work closely with DFT Tool Vendors and drive improvements based on the testability requirements
Develop efficient DFx flows and methodology compatible with front end and back end design flows
Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement
Mentor and coach junior engineers

Fulltime

Principal Design Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
9+ years of experience in creating simulation environments, developing tests, and debugging for multiple silicon IP's or systems
5+ years’ industry experience of chip and/or computer architecture
5+ years industry experience in Verilog or VHDL, C/C++, and scripting language such as Python, Ruby or Perl
CPU or Graphics core verification experience
In depth knowledge of verification principles, testbenches, stimulus generation, System Verilog, UVM, and coverage closure

Job Responsibility

Creation of complex verification environments and tests, pre-silicon functional verification at the block, chip and system level, reference modeling and post-silicon validation
Interact with architects and design engineers to create verification plans covering strategy, test environments & tests, and verification requirements for IP/SS/SOC level verification
Create and drive test-plans and test development to provide complete features coverage
Develop and implement technical solutions to complex quality and design challenges
Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage
Triage and debug testbench, simulation, and emulation fails
Develop Makefiles and scripts for scalable and efficient verification
Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment
Collaborate with teams across sites and geographies

Fulltime

CPU Formal Verification Engineer

Responsible for verifying latest gen complex Ryzen CPU clusters/blocks using for...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s, Master’s, or Ph.D. in Computer Engineering, Electrical/Electronic Engineering, Computer Science, or related field
5–10 years exp in formal verification for logic/microarchitecture IP— preferably CPU-related
Proven experience using formal engines (e.g. JasperGold, VC Formal) for bug hunting
Skilled in assertion languages (SystemVerilog Assertions) and HDL modeling (Verilog/VHDL/SV)
Strong scripting or programming ability (Python, Tcl, Perl)
Analytical mindset with intellectual curiosity
ability to uncover hidden verification gaps
Exceptional communicator and collaborator in cross-functional environments
Mentorship or technical ownership experience—leading reviews and guiding junior engineers

Job Responsibility

Perform formal verification (model checking, equivalence checking) on CPU microarchitecture/IP blocks
Develop formal proofs, abstraction models, and convergence methodologies to maximize coverage and bug hunting
Generate comprehensive formal verification plans: scope, coverage goals, strategy, and proof approaches
Lead ROI analysis to balance formal vs. dynamic methodologies
Work with architects, RTL designers, and verification teams to resolve failing assertions and improve design quality
Look for potential sign-off for critical blocks to guarantee exhaustive proof and reduce silicon escapes
Support post-silicon failure debug and sighting resolution when required
Maintain and enhance formal infrastructure (flows, abstraction techniques, tools)
Investigate new formal techniques and define reusable verification methodologies for the team

Head of Design Verification, Interface IP

We are hiring a Head of Design Verification – Interface IP to own and scale veri...

Location

United States , San Jose

Salary:

200000.00 - 300000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

10+ years of design verification experience with ownership of complex IP or SoC subsystems
Deep hands-on expertise in SystemVerilog and UVM
Strong understanding of SoC mCPU design and high-speed interfaces (PCIe, Ethernet, AXI/AMBA)
Tape-out experience with final DV sign-off responsibility
Systems-level DV mindset
Comfortable being hands-on in a fast-moving startup environment

Job Responsibility

Own end-to-end DV strategy and sign-off for Interface IP across Etched SoCs
Act as the technical authority on correctness, protocol compliance, performance, and robustness
Lead DV for CPU subsystems (boot, interrupts, coherency, system control)
Lead DV for high-speed interfaces, including throughput and latency verification
Architect and evolve SystemVerilog/UVM verification environments
Drive vendor IP integration, configuration reviews, and verification gap closure
Partner closely with architecture, RTL, SoC DV, and software teams
Hire, mentor, and lead a small, high-impact Interface IP DV team
Advise the strategy and execution of emulation testing for pre-silicon validation

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Principal Engineer, RTL Design

Enphase is looking for an experienced SoC and IP Subsystems design engineer to w...

Location

India , Bangalore

Salary:

Not provided

Enphase Energy

Expiration Date

Until further notice

Requirements

Deep understanding and experience in SoC micro architecture, IP Development, RTL and integration
Specific experience integrating the ARM CM4 and all the surrounding IP, like: AHB, AXI, RAM and ROM controllers, DMA controllers
Experience with the ARM Protection units is preferred
Experience with one of the “TrustZone” like IP from other vendors will be an added advantage
Experience with integrating high speed and high accuracy analog systems is a must
RTL Integration of SoC/Subsystems from IPs, ability to debug the issues in logic verification, act as liaison between Design and Place and Route teams is mandatory
Knowledge of all the Soft IP collateral and deliverables eg: Lint, CDC, UPF, timing constraints
Experience and ability to shape and direct our future IP and SoC integration methodology

Job Responsibility

Architect, design and integrate our CPU Subsystem or peripheral Ips into our next generation of MCUs, including the safety and security features that are required by our applications
Responsible for defining the verification plans for these subsystems

Senior SoC Performance Verification Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience
OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
BS/MS in Electrical Engineering, Computer Engineering, Computer Science or related degree.
Performance verification experience through at least one end-to-end tapeout.
6+ years of experience working on Computer Architecture and SoC design and verification principles, including using industry standard HDLs like System Verilog/UVM.
Experience developing tests targeting emulation platforms, including C/C++ and accelerated VIP content.

Job Responsibility

Own a novel performance verification endeavor, driving methodology for the current and future Cobalt programs.
Work with performance, IP, and SoC architects to identify and correlate on key performance indicators.
Become knowledgeable on the overall SoC architecture, understanding performance-critical datapaths and configurations.
Develop verification strategy, test plans, requirements, environments, tools, and methodologies.
Create performance tests, debug correlation mismatches to root cause, and recommend fixes.
Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably.
Mentor and coach team members
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers.
Embody our culture and values.

Fulltime

Senior SoC HW (Functional) Validation Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Hillsboro

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Applied understanding of Computer Architecture and CPU/SoC validation principles, including: Understanding of SoC subsystem, SoC system level, and platform level functionality and writing scripts/software with industry standard languages like Python or C/C++
At least 5+ years of experience
Proficient communication, collaboration and teamwork skills and ability to lead, grow, and contribute to diverse and inclusive teams
Verification, logic development, validation, or validation tools experience as part of a CPU, SoC and/or IP development team
Leadership skills
Demonstrated validation expertise in one or more of the following: Functional: Core, cache Coherency/mesh/fabric, PCIe/ IO, Memory Controller, Power Management
Power and Performance
Automation, Content Creation, or Tools/Scripts Development

Job Responsibility

Own post-silicon validation of one of the following areas – functional validation of cache Coherency/mesh/fabric
Define, guide, and contribute to the implementation of silicon debug tools and capabilities
Become an expert on the overall architecture, implementation of complex features/flows/protocols, and their interactions with other parts of the SoC, with the platform, and with software
Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise
Develop validation strategy, requirements, environments, tools, and methodologies including debug board and hardware/software requirements
Apply your knowledge of validation principles and techniques and your judgement to write test plans and implement them by developing test content, scripts, tools and other validation collateral
Execute content in post-silicon, triage and debug failures
Apply your growth mindset to learn and adapt in a complex and dynamic environment
Engage with partners to drive continuous improvement to the design, to validation plans/collateral, and methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably
Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, verification engineers, other post-silicon validators, and IP and tool providers

Fulltime

CPU Design Verification Architect

AMD

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
April 05, 2026

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Job Description:

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