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CPU Architecture and RTL Design Lead Engineer

Ireland, Cork · Job Posted April 16, 2026
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Job Description

Drive the definition, implementation (RTL design), and integration of Clocking, Reset and Power in AMD’s next-generation core. Work as part of an experienced, skilled, and motivated engineering team to help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.

Job Responsibility

  • Collaborate with a dedicated team of engineers to define and implement CPL microarchitecture for AMD CPUs
  • Reliably deliver a design from concept through tapeout
  • Drive design closure gaining experience with Static Timing, CDC/Gate CDC, and Static Power analysis
  • Identify customer challenges and insert a compelling AMD value proposition to address challenges
  • Make technical contributions and innovations that enable high performance, high frequency, and power efficiency on caches, fabrics, and interfaces of our server, desktop, and laptop CPUs

Requirements

  • Proficiency with Verilog HDL
  • Understanding of Clock/Power Domain Crossing concepts
  • Understanding of Power Management concepts
  • Understanding of modern CPU architecture
  • Eagerness to learn and grow as a CPL design engineer
  • Collaborate effectively towards the success of the project
  • Demonstrate a responsive track record of engaging with a diverse set of teams and across a broad set of technical areas
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Nice to have

Prior experience designing shared cache or last level cache and related IPs

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