CPU Architecture and RTL Design Lead Engineer Job at AMD (Cork)

Lead RTL Design Engineer

As a lead front-end design engineer, you will be a key part of the world-class t...

Location

United States , Sunnyvale

Salary:

175000.00 - 275000.00 USD / Year

Cerebras Systems

Expiration Date

Until further notice

Requirements

Master’s degree in Computer Science, Electrical Engineering, or equivalent
8-15 years of experience in delivering complex, high performance high quality RTL designs
Experience with Front End Chip integration and third-party IP integration
Demonstrated experience in networking, high-performance computing, machine learning or related fields
Proven track record of multiple silicon success
Experience collaborating and managing external vendors
Experience with designing/integrating high speed IO
Networking stack experience including TCP/IP, RDMA and Ethernet
Knowledge of PCIe, CPU interfaces and Serdes technology
Working knowledge of scripting tools : Python, TCL

Job Responsibility

Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis
Managing external ASIC vendor through product development cycle
Work closely with PD team members for design closure to meet PPA goals
Work closely with Design verification and DFT teams for achieving the best functional and test coverage
Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product
Debug silicon-level functional, timing, and power issues during bring up

What we offer

Build a breakthrough AI platform beyond the constraints of the GPU
Publish and open source their cutting-edge AI research
Work on one of the fastest AI supercomputers in the world
Enjoy job stability with startup vitality
Our simple, non-corporate work culture that respects individual beliefs

Fulltime

Technologist, ASIC Development Engineering (RTL Design and SoC architecture, Lint)

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Physical Design Lead - CPU

As a member of the Radeon Technologies Group, you will help bring to life cuttin...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelors or Masters degree in computer engineering/Electrical Engineering
Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAX
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design

Job Responsibility

Implementation and verification of DFT architecture and features
Scan insertion and ATPG pattern generation
ATPG patterns verification with gate-level simulation
Test coverage and test cost reduction analysis
Post silicon support to ensure successful bring up and enhance yield learning

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Physical Design Lead - CPU Team

The position will involve working with a very experienced CPU physical design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

CPU Physical Design Lead

The position will involve working with a very experienced CPU physical design te...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

8+ years of professional experience in physical design, preferably with high-performance designs
Must have closed high-performance IPs- CPU/GPU/DPU/memory controller, etc.
Strong experience with tools for logic synthesis, place and route, timing analysis, and design checks for physical and electrical quality
familiarity with tools for schematics, layout, and circuit/logic simulation
Versatility with scripts to automate design flow - Perl/Tcl/Python
Strong communication skills, ability to multi-task across projects, and work with geographically spread out teams
Experience in advanced sub 7nm nodes
Excellent physical design and timing background
A good understanding of computer architecture is preferred
Strong analytical/problem-solving skills and pronounced attention to detail

Job Responsibility

Own critical CPU units and drive to convergence from RTL-to-GDSII - synthesis, floor-planning, place and route, timing closure, and signoff
Understand the micro-architecture to perform feasibility studies on performance, power, and area (PPA) tradeoffs for design closure
Develop and improve physical design methodologies and customize recipes across various implementation steps to optimize PPA
Implement floor plan, synthesis, placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC & LVS), EM/IR and signoff
Handling different PNR tools - Synopsys fusion compiler, Cadence, PrimeTime, StarRC, Calibre, Apache Redhawk

Senior Staff Physical Design Engineer

We are looking for an adaptive, self-motivative physical design engineer to join...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience and specialization in deep‑submicron ASIC physical design, including all phases from RTL-to-GDSII and signoff
Proven record of Physical Design signoff flow
Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Tempus, PrimeTime, Fusion Compiler, Calibre)
Excellent scripting skills in TCL, Shell, Python, or Perl to enhance PD flows and automation
Proven ability to work with cross-functional teams across multiple sites/time zones
Strong analytical, problem-solving, and communication skills
Familiarity with CPU and or GPU architecture
Proficiency in data analysis and interpretation

Job Responsibility

Static Timing Analysis (STA) across MMMC scenarios: Driving timing closure at block and full‑chip levels, resolving violations through ECOs, constraint refinements, and reviewing SoC and block‑level signoff readiness. Lead timing signoff (setup, hold, OCV, AOCV/POCV, SI, CDC interfaces) across all modes and corners
Logic Equivalence Check (LEC) for all blocks and full‑chip: Executing equivalence verification between RTL, synthesis, and P&R databases
Low‑power structural checks (UPF/CLP): Ensuring correctness of power‑intent implementation, power‑domain crossings, isolation/retention, and coverage of low‑power signoff flows
Physical Integrity Signoff: Overseeing DRC/LVS structural verifications, and ensuring designs adhere to foundry signoff rules. Perform and review IR drop, EM, and power integrity signoff
Clocking and top‑level mesh implementation and signoff
Own and drive block-level and/or full-chip physical implementation and signoff to tape-out
Analyze complex cross-block and top-level signoff issues and define closure strategy
Define and enforce signoff criteria, methodologies, and best practices
Partner with PD implementation teams to guide ECO strategy for timing, power, and physical fixes
Identify risk areas early and proactively drive mitigation plans

Staff/Principal Design Engineer - Video

The Systems Media IP group is responsible for the development of Image Signal Pr...

Location

United Kingdom , Manchester; Cambridge; Bristol

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

Experience in ASIC RTL design, ideally for Multimedia IP (ISPs, DPUs, VPUs) or related IP (CPU, GPU, interconnect, memory controllers, high-performance peripherals)
Proficiency in System Verilog, Verilog or VHDL
Exposure to all stages of design: concept, specification, implementation, testing, documentation, and support
Proficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting
Prior technical and/or team leadership skills required for more senior positions

Job Responsibility

Ownership of unit level development or multiple unit hierarchy or technical lead of an overall IP
Design and test new hardware modules to implement innovative imaging algorithms and/or video codecs
Engage in all aspect of hardware design including architectural investigations and modeling, specifications, design and simulation, backend implementation support and IP maintenance
Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance the hardware design efficiency
Collaborate closely with colleagues in the verification teams, modelling teams, software driver developers, multimedia architects and imaging researchers
Mentor & support other members of the team

What we offer

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CPU Architecture and RTL Design Lead Engineer

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