CPU Architecture and RTL Design Lead Engineer Job at AMD (Cork)

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Rtl design lead - cpu team

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

6+ years of experience in Digital IP/ASIC design and Verilog RTL development
Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
Should possess expertise in front-end EDA tools sign-off and its flows
Familiarity with low power design and low power flow is an added plus
Ability to program with scripting languages such as Python or Perl is a plus
Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
Proven interpersonal skills, leadership and teamwork
Excellent writing skills in the English language, editing and organizational skills required

Job Responsibility

RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
Architect and design of power management features, cache, coherency
Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
Responsible for the inter IP integration issues resolution
Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
Architecting, micro-architecting and documentation of the design features
Lead design team from all aspects of the RTL deliverables
Mentor the junior members of the RTL team to meet the team goals
Represents AMD to the outside technical community, partners and vendors

Senior RTL Design Lead

We are seeking a seasoned Principal design engineer with expertise or significan...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent foundation in fabric/transport architecture and coherency
Experience in memory design/cache design
Bachelor’s or Master’s degree in computer engineering/Electrical Engineering
Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
Excellent communication, management, and presentation skills
Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies

Job Responsibility

Define Data Fabric features and capabilities required to meet SoC requirements on power, performance, Area targets
Digital design implementation and micro-architecture of components of the Infinity Data Fabric, including cache design
Micro-architecture and RTL coding in Verilog/SystemVerilog
Lead design on one or more domains
Work with architects and design leads to identify and assess complex technical issues
Work closely with verification teams to ensure quality component development
Work closely with Physical design to ensure quality PPA targets
Post silicon support to ensure successful bring up
Define product features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications for SoC and IP blocks to meet those requirements, and provide technical direction to execution teams
Comprehend the SOC as a complete system which includes HW (Silicon), FW, BIOS & SW and ensure that FW, BIOS & SW are aligned to enable all features, optimizing for performance and power

Technologist, ASIC Development Engineering (RTL Design and SoC architecture, Lint)

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff/Principal Design Engineer - Video

The Systems Media IP group is responsible for the development of Image Signal Pr...

Location

United Kingdom , Manchester; Cambridge; Bristol

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

Experience in ASIC RTL design, ideally for Multimedia IP (ISPs, DPUs, VPUs) or related IP (CPU, GPU, interconnect, memory controllers, high-performance peripherals)
Proficiency in System Verilog, Verilog or VHDL
Exposure to all stages of design: concept, specification, implementation, testing, documentation, and support
Proficiency in UNIX and scripting languages such as TCL, Perl, Python, or shell scripting
Prior technical and/or team leadership skills required for more senior positions

Job Responsibility

Ownership of unit level development or multiple unit hierarchy or technical lead of an overall IP
Design and test new hardware modules to implement innovative imaging algorithms and/or video codecs
Engage in all aspect of hardware design including architectural investigations and modeling, specifications, design and simulation, backend implementation support and IP maintenance
Identify cross Media IP process or methodology improvement opportunities, implementing changes to advance the hardware design efficiency
Collaborate closely with colleagues in the verification teams, modelling teams, software driver developers, multimedia architects and imaging researchers
Mentor & support other members of the team

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

Senior Silicon Engineer

Microsoft is a highly innovative company that collaborates across disciplines to...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

10+ more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl

Job Responsibility

Own or lead verification of complex flows at the SOC, subsystem, or IP levels
Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
innovate to improve verification efficiency through methodologies or tools
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

Principal Verification Engineer

Microsoft is a highly innovative company that collaborates across disciplines to...

Location

India , Bangalore

Salary:

Not provided

Microsoft Corporation

Expiration Date

Until further notice

Requirements

12+ more years of experience in design verification with a proven track record of delivering complex CPU or SoC IP’s
Experience with verification for multiple product cycles from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff in UVM or C++
Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments
Scripting language such as Python or Perl

Job Responsibility

Own or lead verification of complex flows at the SOC, subsystem, or IP levels
Plan the verification of complex design IP/SoC interacting with the architecture and design engineers to identify verification test scenarios
Learn about the design and interact with partner teams to define verification strategies and test plans
Develop verification environments and run and debug simulations to drive quality
Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
innovate to improve verification efficiency through methodologies or tools
Coach and mentor others in your areas of expertise
Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Fulltime

CPU Architecture and RTL Design Lead Engineer

AMD

Location:
Ireland , Cork

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
April 16, 2026

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