CrawlJobs Logo

Chip Lead

etched.com Logo

Etched

Location Icon

Location:
United States , San Jose

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

250000.00 - 300000.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

We are looking for a Chip Lead to take full technical ownership of our next silicon program from architecture through production. This role is for a senior, hands-on leader who has shipped complex chips and is comfortable being the final technical authority on key decisions. You will act as the single threaded owner of the chip, setting technical direction, reviewing designs in detail, and driving the organization to a successful tapeout, bring-up, and production ramp.

Job Responsibility:

  • Own the silicon from architecture definition through RTL, physical design, tapeout, bring-up, and production
  • Be accountable for the chip meeting performance, power, area, quality, cost, and schedule targets
  • Serve as the final technical escalation point for all chip-level issues
  • Define and review the top-level SoC architecture, including block partitioning, interconnects, clocks/resets, power domains, and interfaces
  • Drive key architectural and microarchitectural tradeoffs and ensure alignment with system-level requirements
  • Ensure robustness, testability, and manufacturability are built into the design from the start
  • Actively review RTL, verification plans, physical design closure, DFT, and test strategy
  • Challenge assumptions and drive simplification where possible
  • Hold a high bar for design quality, correctness, and clarity
  • Drive technical readiness for tapeout
  • Make clear go/no-go calls and tradeoff decisions when necessary
  • Lead post-silicon bring-up and debug, working closely with firmware, software, and validation teams
  • Drive rapid learning on first silicon and lead root-cause analysis for issues
  • Partner with manufacturing and test teams on yield, reliability, and production ramp
  • Own the transition from first silicon to stable, high-volume production
  • Work directly with foundries, OSATs, and IP vendors on technical execution
  • Collaborate closely with system, board, and product teams to ensure silicon success
  • Communicate technical status, risks, and decisions clearly to leadership

Requirements:

  • 10+ years of semiconductor design experience
  • Proven experience shipping at least one complex SoC or ASIC into production
  • Strong technical depth across the full silicon lifecycle, including: SoC architecture and microarchitecture, RTL design and verification, Physical design, timing, power, and closure, DFT, test, yield, and reliability, Post-silicon bring-up and debug
  • Ability to dive deep into details while maintaining chip-level perspective
  • Strong technical judgment and ownership mindset

Nice to have:

  • Prior experience as a Chip Lead, SoC Lead, or senior technical lead at a top-tier semiconductor company
  • Experience with high performance compute, AI accelerators, or large-scale SoCs
  • Experience with advanced nodes and/or advanced packaging
  • Familiarity with CoWoS or other 2.5D/3D packaging technologies
What we offer:
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Plus Significant Equity

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Icon
Etched - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon
PREMIUM
More languages and countries
+ Unlock 31694 hidden job offers
Languages
English Čeština Deutsch Ελληνικά Español Français +15
Countries
United States United Kingdom India Canada Australia +
See plans
Plans from $2.99 / month

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Chip Lead

Physical Design Engineer

This role has been designed as ‘Hybrid’ with an expectation that you will work o...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 4+ years experience in ASIC physical design
  • Experience with block implementation, extraction, timing and or full-chip designs
  • Strong communication skills
  • Strong hands-on TCL/Perl development skills
  • Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
  • Track record of taping out complex chips on advanced process nodes
Job Responsibility
Job Responsibility
  • Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
  • Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow
  • Experienced in design automation
  • Understanding of Timing constraints, SI prevention, Power reduction
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

Technologist lead full chip soc sign-off emir closure engineer

The candidate to have a passion for complex processor architecture, digital desi...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Minimum 8 to 12 years of relevant work experience
  • Expertise in Synthesis, ICC2/FC (Fusion Compiler) Physical Design flows/methodologies or equivalent tools
  • Expertise in Signoff tools like Ansys Redhawk/RHSC on EMIR, PT-PX for Power signoff and Primetime for Timing
  • Should have worked as a go to person or technical lead for at least few full chip projects
  • Strong technical leadership and ability to mentor/guide/coach design engineers
  • Strong inter-personal skills and ability to collaborate with teams spread across multiple geos
  • Should have good scripting experience in Shell, Python, Perl, TCL, UNIX
  • Must be using AI technologies in day to day problem solving
  • Bachelors or Masters degree in Electronics and communication engineering/Electronics and Electrical Engineering
Job Responsibility
Job Responsibility
  • EMIR closure at Tile /Partition/Subsytem/SOC level on a particular node
  • Ownership of EMIR Flow & Signoff
  • Drive EMIR closure for design blocks and full-chip integration
  • Align EMIR analysis phases with PD milestones (INIT, PREFINAL, FINAL)
  • Ensure compliance with signoff limits provided by SIPI team for given technology node
  • Ability to analyze EMIR violations and propose implementation choices
  • Familiarity with DFx and scan architecture for EMIR considerations
  • Define EMIR signoff strategy, including IR drop and electromigration analysis
  • Review floorplan, clocking, and bus structures for IR hotspots
  • Coordinate bump allocation and power rail alignment with integration teams
  • Fulltime
Read More
Arrow Right

Platform Architect

As a Platform Architect, you will lead the definition and realization of our AI ...
Location
Location
United States , San Jose
Salary
Salary:
150000.00 - 275000.00 USD / Year
etched.com Logo
Etched
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ years of experience in system or server hardware architecture, ideally in HPC, AI infrastructure, or hyperscale data centers
  • Deep understanding of PCIe protocols and topologies, including bifurcation, retimer tuning, switch fabrics, and accelerator communication
  • Experience with rack-level and multi-rack system design, including shared power and networking infrastructure
  • Strong expertise in BMC systems, control buses, telemetry integration, and orchestration tooling
  • Familiarity with modern high-speed networking technologies: 400G Ethernet, InfiniBand, CXL fabrics, and NIC-switch integration
  • Proven background in power architecture for dense compute systems, including power budgeting, sequencing logic, and VRM optimization
  • Rack-level management infrastructure design experience, including CDU layout, telemetry aggregation, and rack controller implementation
  • Proven track record of building infrastructure for at-scale deployment, such as automated diagnostics, health monitoring, and fleet orchestration frameworks
  • Understanding of thermal design principles such as airflow, heatsink selection, and liquid cooling systems
  • A systems-level perspective with the ability to design scalable, maintainable, and high-performance platforms
Job Responsibility
Job Responsibility
  • Architect the end-to-end hardware system stack, including server-level components, rack-scale systems, and multi-rack POD designs optimized for AI and high-performance workloads
  • Design and implement advanced PCIe Gen5/Gen6 topologies: root complex architecture, retimer placement, switch hierarchy, and accelerator fan-out strategies
  • Define scalable BMC architecture and platform management features across fleet deployments, including telemetry pipelines, orchestration hooks, and API integrations (e.g., Redfish, IPMI)
  • Specify and lead the implementation of chip-to-chip interconnects such as NVLink, UCIe, and other emerging high-bandwidth, low-latency fabrics
  • Develop integration strategies for power distribution, control planes, cooling systems (air and liquid), and shared interconnect fabrics at the rack level
  • Own the networking architecture across servers and racks, including 400G/800G Ethernet, leaf-spine switching, NIC-to-ToR planning, and cross-rack topology
  • Specify power delivery systems for high-density, multi-kilowatt platforms: VRM selection, power trees, sequencing, and protection logic
  • Guide system design decisions with awareness of mechanical and thermal constraints to ensure performance, manufacturability, and serviceability
  • Contribute to rack-level management infrastructure: CDU planning, telemetry aggregation, rack controller architecture, and out-of-band control
  • Support bring-up and validation teams in debugging complex issues at the system, rack, and POD levels
What we offer
What we offer
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Fulltime
Read More
Arrow Right

Silicon System Validation Engineer

Meta's Silicon Engineers are at the forefront of innovation, driving the design ...
Location
Location
Taiwan , Taipei
Salary
Salary:
Not provided
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of hands-on experience in the bring-up and validation of complex System-on-Chip (SoC) components
  • Experience leading silicon validation planning, execution, firmware development for validation, and validation sign-off processes
  • Demonstrated experience with high-speed protocols, such as MIPI, PCIe, USB, and DDR, including hands-on experience in high-speed input/output (IO) bring-up
  • Demonstrated experience using laboratory equipment, including oscilloscopes, bit error rate testers (BERTs), protocol analyzers, and JTAG debuggers
Job Responsibility
Job Responsibility
  • Lead the development, execution, and sign-off of System-on-Chip (SoC) and end-to-end system validation plans
  • Identify and communicate technical risks related to silicon validation projects to relevant stakeholders
  • Plan, organize, and oversee silicon bring-up and validation activities across multiple SoCs
  • Execute and coordinate test and debug activities with cross-functional and plug-and-play (PnP) teams, ensuring thorough validation coverage
  • Lead laboratory debug activities, silicon bug reproduction, failure analysis, and failure reporting across multiple domains or projects
  • Work with cross-functional teams (i.e., architecture, intellectual property (IP), firmware (FW), electrical engineering (EE), SoC, and product engineering teams to generate comprehensive validation reports for SoC and system-level components
  • Work in an agile environment, adapting roadmaps and validation plans based on changing requirements
What we offer
What we offer
  • Meta offers benefits
  • Fulltime
Read More
Arrow Right

Silicon System Validation Engineer

Meta's Silicon Engineers are at the forefront of innovation, driving the design ...
Location
Location
Taiwan , Taipei
Salary
Salary:
Not provided
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of hands-on experience in the bring-up and validation of complex System-on-Chip (SoC) components
  • Experience leading silicon validation planning, execution, firmware development for validation, and validation sign-off processes
  • Demonstrated experience with high-speed protocols, such as MIPI, PCIe, USB, and DDR, including hands-on experience in high-speed input/output (IO) bring-up
  • Demonstrated experience using laboratory equipment, including oscilloscopes, bit error rate testers (BERTs), protocol analyzers, and JTAG debuggers
Job Responsibility
Job Responsibility
  • Lead the development, execution, and sign-off of System-on-Chip (SoC) and end-to-end system validation plans
  • Identify and communicate technical risks related to silicon validation projects to relevant stakeholders
  • Plan, organize, and oversee silicon bring-up and validation activities across multiple SoCs
  • Execute and coordinate test and debug activities with cross-functional and plug-and-play (PnP) teams, ensuring thorough validation coverage
  • Lead laboratory debug activities, silicon bug reproduction, failure analysis, and failure reporting across multiple domains or projects
  • Work with cross-functional teams (i.e., architecture, intellectual property (IP), firmware (FW), electrical engineering (EE), SoC, and product engineering teams to generate comprehensive validation reports for SoC and system-level components
  • Work in an agile environment, changing roadmaps and adapt to validation plans based on changes
Read More
Arrow Right

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...
Location
Location
United States , Mountain View
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
  • Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
  • Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
  • equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
  • Experience in tapeouts of complex ASICs in leading edge technology
  • Experience in leading team to deliver planned PD goals
Job Responsibility
Job Responsibility
  • Lead and execute Physical Design activities at block, sub-chip, and full-chip levels
  • Contribute to Physical Design flow development, automation, and methodology improvements
  • Evaluate and recommend technology nodes, IP selection, EDA tools, and vendor solutions
  • Provide clear and concise status updates on progress, risks, and mitigation plans to management
  • Operate independently with minimal supervision while maintaining strong attention to detail
  • Support program needs, including occasional travel as required
  • Drive all phases of implementation including: Floorplanning
  • Synthesis
  • Placement and optimization
  • Clock Tree Synthesis (CTS) and custom clocking
  • Fulltime
Read More
Arrow Right

Postdoctoral Researcher in Analogue Mixed-Signal Design

Postdoctoral Researcher in Analogue Mixed-Signal Design for Power Management Int...
Location
Location
Ireland , Cork
Salary
Salary:
46805.00 - 53391.00 EUR / Year
tyndall.ie Logo
Tyndall National Institute
Expiration Date
May 22, 2026
Flip Icon
Requirements
Requirements
  • PhD in electrical/electronics engineering, science or related discipline with experience in Analogue Circuit Design applied to Power Management Integrated Circuits (PMICs)
  • Significant industry or research experience in analogue IC design in building blocks for Power Management Integrated Circuits, such as micro-to-multi-ampere power path design (linear and switched type), amplifier design, analogue mid/low-voltage (48V-0.6V) sensing or data converters (A/D, D/A) sensing, reference generators, clocking generation (PLL, DLL) with low Electromagnetic Interference (EMI), mixed signal analogue circuit calibration techniques
  • Strong knowledge of CMOS, FD-SOI IC CAD design tools and circuits, including voltage references, parameter-optimized amplifiers (e.g.: low noise, high power supply rejection) for voltage/current sensing, data converters (A/D, D/A), voltage converters and/or regulators
  • A strong publication and / or patent record in the field of analogue integrated circuit design for PMICs
  • Demonstrated ability to work alone and to work in technical teams and lead a chip design project
  • Experience of bringing analogue IC design projects all the way through the design flow through final chip tape-out to wafer fabrication and to laboratory test measurement validation stage
  • Good record in delivering IP developments in Analogue Mixed-Signal IC Design for PMICs
  • The successful candidate will be highly innovative and analytical with a strong desire to create world-beating PMIC research for real-life Industry applications
Job Responsibility
Job Responsibility
  • Act as key contributor in the development of state-of-the-art power management ICs (PMICs), covering system-level simulation, algorithm design, schematic/layout and silicon validation, in collaboration with MCCI industry and research partners
  • Carry out innovative research in Analogue Mixed-Signal IC Design, with a focus on taking advantage of deep-submicron CMOS and FD-SOI technologies to reduce power losses, improve efficiency and improve voltage regulation in PMIC platforms
  • Develop and maintain existing research partnerships, while also building new relationships
  • Participate and manage research proposals to attract national, international and industry funding
  • Perform modelling and analysis on the limitations of existing PMIC solutions
  • Support research projects led by the Group Head, designing PMIC architectures and circuits in analogue/digital control loops, precision voltage/current sensing, data converters (A/D, D/A) and PMIC interfaces, i.e.: SPI, I2C, LVDS, SerDes
  • Engage in the dissemination of the research results, as directed by and with the support of senior MCCI research staff, in key international journals, conferences and workshops
  • This also extends participation in education and public engagement activities to promote science and engineering technologies, to schools and the public
  • Report to the MCCI Principal Investigator (PI) for Integrated Power
  • Engage in appropriate training and development opportunities to develop personal transferable skills, career and reputation
What we offer
What we offer
  • Access to UCC pension
  • Long-term illness benefit
  • Life assurance
  • Competitive annual leave entitlements
  • Equity & Inclusion
  • Core Values: Ambition, Collaboration, Diversity, Excellence, and Integrity
  • Entrepreneurial Spirit
  • Supportive Onboarding
  • Blended Working
  • Continuous Learning
  • Fulltime
!
Read More
Arrow Right
New

R&D Product Development Scientist

Overview We Are PepsiCo PepsiCo is a leading name in North Africa’s food and bev...
Location
Location
Egypt , New Cairo
Salary
Salary:
Not provided
pepsico.com Logo
Pepsico
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Very strong innovation skills are required, in particular through strong data analysis (incl. competitive intelligence, insights) and ability to ‘connect the dots’ from incomplete set of data and hypothesis
  • Proven R&D product development experience preferred
  • Experience in project management and stakeholder management
  • Proven and impactful records of successfully influencing their network (R&D organisation, Supply chain) to deliver successful innovation in Adjacent Categories
  • Experience in working with external interfaces (for this particular role mainly include strategic OEM’s, suppliers, academia and external technical consultants)
  • Able to travel to African Countries (Ethiopia, Nigeria and Zibabwe), and have an understanding of how to work well with different cultures and diverse groups
Job Responsibility
Job Responsibility
  • Leverage a combination of functional and business expertise to develop the technical elements of winning consumer propositions that drive sustainable business growth and support the required BU Innovation Strategy
  • Leveraging expertise inside and outside the organisation to deliver product and process development
  • Take full ownership and accountability of the technical activities with a strong focus on extrusion and potato chips technology leading to core capabilities and critical expertise
  • Project leadership to develop and execute new advancements in extrusion projects utilising solid technical project management tools and skills to ensure objectives are accomplished on time, to the agreed standards and within budget
  • Managing, planning and execution of trials on manufacturing and pilot plant scale, including troubleshooting and the completion of relevant project documentation (Technical Stage Gate – TSG)
  • Deputise as required for the R&D Manager to represent R&D interest at key forums (e.g. PTM’s)
  • Take accountability of identifying technical solutions for BU calendar activities
  • Manage raw material suppliers, to lead work programmes on behalf of PepsiCo
  • Mobility is a must, required to conduct trials and line validation across Africa (currently Ethiopia, Nigeria and Zimbabwe)
  • Regular contact with the R&D Manager
  • Fulltime
Read More
Arrow Right