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This position for a CAD Engineer will be critical to shaping the next generation AMD products, the leader in GPU, CPU. It requires interfacing with large design teams across the globe and owning development & support for next generation synthesis, place and route flows. Successful candidate would be responsible for automation of PnR flows and methodologies for the 3nm & 2nm technology nodes as well as working closely with the EDA vendors to identify innovative solutions and track methodology issues.
Job Responsibility
Responsible for developing Place and Route methodologies for various designs at advanced technology nodes
Work seamlessly with synthesis and signoff (STA, extraction, Physical Verification) teams to achieve best-in-class PPA
Drive power/performance/area (PPA) convergence for SOCs implementation
Script out utilities to automate different pieces of the implementation flow
Support design teams at global sites through multiple PnR flow stages including chip finish flows
CAD flow and Methodology development on advanced process nodes such as 3nm, 2nm are preferred
Requirements
Hands‑on experience in PNR flows including multi-voltage & power-gated designs
Expertise with industry‑standard physical design tools Fusion Compiler and/or Innovus
Experience with synthesis, STA, Physical verification domains is a plus
Strong understanding of low-power flows includes UPF concepts, power-gating, isolation, level-shifter, voltage_areas, power-state tables, electrical checks using FM & VSI
Proficiency in scripting and automation using Python, TCL, and Perl with strong debugging capabilities and CAD‑automation mindset
Exposure to AI/ML concepts, with strong Python proficiency
CAD and Automation mindset
Master’s/Bachelor’s Degree in Electronics Engineering (Minor in Computer Science preferred)
8-10 years of experience in CAD flow and methodology development on advanced nodes such as 3nm & 2nm