Asic verification manager Job at Hewlett Packard Enterprise (Roseville)

Vlsi Design Verification Manager - Slingshot Asic Team

Hewlett Packard Enterprise is seeking a VLSI Design Verification Manager to lead...

Location

United States , Ft. Collins

Salary:

142000.00 - 270000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent
Typically 10+ years of experience in VLSI design verification, with strong hands-on background in pre-silicon DV
Strong understanding of SystemVerilog and UVM-based verification methodologies
Demonstrated technical leadership in design verification
Ability to lead engineers through influence, technical credibility, mentorship, and clear communication
Experience with verification planning, coverage-driven verification, regression management, and sign-off readiness
Proficiency with DV workflows using industry EDA simulation tools
Strong analytical and problem-solving skills
Excellent written and verbal communication skills
Ability to operate effectively in a multi-site, cross-functional engineering environment

Job Responsibility

Provide leadership and direction for a team responsible for all phases of pre-silicon design verification, including verification planning, testbench development, coverage closure, regression management, and sign-off reviews
Define, own, and evolve design verification methodology, ensuring consistent, high-quality verification practices across block, subsystem, and full-chip scopes
Ensure development of robust SystemVerilog/UVM-based environments, including stimulus, scoreboards, checkers, assertions, and functional coverage
Drive regression health, failure triage, root-cause isolation, and closure of design issues in close collaboration with logic design and architecture teams
Manage project deliverables, schedules, and staffing to meet program milestones and quality goals
Recruit, mentor, and develop engineers
set performance expectations and support career growth across junior through senior levels
Identify and drive opportunities for process improvement, reuse, automation, and efficiency in verification workflows
Communicate verification status, risks, and readiness clearly to management and cross-functional partners

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Verification Manager

At Codasip, we're redefining the future of computing. Following a bold strategic...

Location

United Kingdom , Bristol

Salary:

Not provided

Codasip GmbH

Expiration Date

Until further notice

Requirements

Extensive experience in semiconductor Verification with a desire to transition to the manager stream
Significant commercial experience with a variety of functional processor verification methodologies as applied to CPU or other ASIC verification (simulators, coverage collection, gate level simulation, etc.)
Knowledge of verifying CPU architectures or other complex IPs (GPUs, NNAs)
Proven ability to manage workload effectively and prioritize tasks in a dynamic environment
Excellent leadership and communication skills, with the ability to motivate and inspire teams
Understanding of RISC-V Architecture
Knowledge of computer systems and architecture
Experience with advanced verification techniques

Job Responsibility

Lead the expansion of our Verification team and capacity over multiple Design Centers, building on top of established foundations and aligning efforts with company strategy and objectives
Collaborate with other Verification Leads to share responsibilities, ensuring effective management of workload and resources
Verify RISC-V processors and extensions
Take ownership of IP Verification projects
Contribute to determining the company's strategy regarding verification
Tackle the challenges unique to Codasip and its customizable IP portfolio
Provide technical leadership and guidance to the Verification team, building a culture of excellence in Verification methodologies and processes
Partner with cross-functional teams to optimize collaboration and streamline project execution
Stay abreast of industry trends and advancements, leveraging insights to drive innovation and maintain our competitive edge

Fulltime

Dft Design Verification Manager

We are looking for an adaptive, self-motivated DFT design verification engineeri...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven track record of leading ASIC or SoC design verification teams through successful product tape-outs
Strong expertise in SystemVerilog, UVM, C++ and coverage-driven verification methodologies
Deep understanding of computer architecture, digital logic design
Hands-on experience with EDA tools (Synopsys VCS, Verdi)
Debugging and problem-solving skills for complex, multi-clock domain designs
Strong people management and communication skills to drive geographically distributed projects
Debug test failures to determine the root cause
work with design engineers to resolve design defects and correct any test issues
Experience with ATE (Automatic Test Equipment) - ATE test pattern & test flow development, debug, test, and characterization
Design verification experience of High-Speed IO PHY and Controller logic is preferred

Job Responsibility

Design verification of High-Speed IO IP DFT features (e.g., JTAG 1149.x, IJTAG, MBIST, Scan, PRBS, IO Loopback, etc.)
Lead and manage a team of design verification engineers, providing technical direction, mentorship, and performance feedback
Define and drive verification strategy for DFT features, ensuring alignment with architectural goals, schedule, and quality targets
Oversee test plan creation, review, and execution for block- and system-level verification
Collaborate with design, architecture, and ATE engineering teams to resolve complex technical issues and optimize verification approaches
Prioritize and allocate resources across multiple verification tasks and projects, balancing execution speed with quality
Provide technical support to SoC and Post-Si teams to ensure successful bring up and enhance yield learning

Fulltime

Sr. Manager ASIC

Annapurna Labs designs silicon and software that accelerates innovation. Custome...

Location

United States , Austin; Cupertino

Salary:

208300.00 - 281800.00 USD / Year

Amazon Pforzheim GmbH

Expiration Date

Until further notice

Requirements

Experience delivering cross functional projects
10+ years of equivalent experience
3+ years of people management experience
Experience leading and interacting with cross-functional teams
Deep technical expertise in SOC integration and methodology
Track record of successful tape-outs in leading edge nodes

Job Responsibility

Lead and grow a team of SOC integration engineers responsible for critical deliverables in our ML accelerator chips
Drive technical decisions across multiple disciplines (RTL, timing, DFT, physical design)
Ensure on-time delivery of complex SOC integration milestones
Establish and maintain best practices for top-level integration, including clock/reset architecture, CDC methodology, and quality metrics
Interface with various stakeholders including architecture, verification, and physical design teams

What we offer

health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
paid time off
parental leave
sign-on payments
restricted stock units (RSUs)

Fulltime

Asic verification lead

Integrating ASIC functional verification team. ASIC developed include network co...

Location

India , Bangalore

Salary:

Not provided

Eviden

Expiration Date

Until further notice

Requirements

Participated in the successful verification of a complex SoC or ASIC
Mastering UVM or equivalent verification methodology
Proficient developer of Constraint-Random / Coverage-Driven verification environments in SystemVerilog / C ++
Strong knowledge of simulation tools and coverage database visualization tools
Developed test plans that helped identifying sharp functional defects
efficiency in problem solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints
Experienced in improving processes and methodologies
Experience in managing tasks for a small team
7 years Required minimum studies
Master/Engineer in Electronics and Communication Engineering

Job Responsibility

Acquire knowledge of the architecture and microarchitecture of the ASIC by studying specifications and interacting with the architecture and logical design teams
Participate in defining overall verification strategies and methodologies, and the required simulation environments. Develop, maintain and publish verification specifications
Write and perform closely test plans with the logical design team
Develop coverage models and verification environments using UVM-SystemVerilog / C ++
Monitor, analyze and debug simulation errors
Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time
Submit recommendations on tools and methodologies to develop to improve productivity. Mentor junior engineers on how to produce a maintainable and reusable code across projects

Senior Manager - ASIC Development Engineering

We are seeking a highly skilled and experienced DFT Engineer to join our dynamic...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

B.Tech / M.Tech / Phd in Electronics, Computer science or Electrical Engineering
Minimum 14+ years of experience in DFT
Strong understanding of DFT Architecture
Extensive experience in SoC DFT architecture, DFT IP development and DFT methodology
Proven track record of driving DFT architecture in complex ASIC designs
Work independently on multiple complex DFT problems across different projects
Proficiency in ASIC DFT Implementation tools, simulation methodologies, and hardware description languages (HDLs)
Proficiency in SCAN, MBIST implementation
Solid understanding of JTAG & BSDL standards
Good understanding on Test clocking requirements, Test mode timing closure

Job Responsibility

DFT Architecture definitions for SoC development
Leading complex activities and providing solutions for complex DFT problems
Collaborate with cross-functional teams to define and refine SoC DFT requirements, ensuring alignment with industry standards and customer needs
Working closely with the Design, Verification, Physical Design & Test Engineering teams while guiding them on the test requirements and methodologies
Work closely with the Product Engineering team and understand the test requirements, get involved in complex silicon debugs
Evaluate all aspects of the SoC DFT flow from requirements, through detailed definitions, and work closely with the CAD to continuously improve the DFT methodology

Fulltime

ASIC Verification Engineer II

We are looking for a new ASIC Verification Engineer to become part of the future...

Location

Costa Rica , Heredia

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
0-4 years of experience in VLSI design, verification or implementation
Experience or understanding of electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
Ability to apply analytical and problem solving skills
Hands-on experience in designing VLSI components, integrated circuitry, architectures and developing algorithms
Knowledge of a programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools
Coursework in VLSI design or VLSI concepts
Good written and verbal communication skills
mastery in English and local language

Job Responsibility

Verifies portions of computer/server architecture and algorithms based on established VLSI engineering principles
Collaborates and communicates with management regarding design status, project progress, and issue resolution
Verifies, simulates, and tests VLSI circuits
Ensures the VLSI designs meet quality, schedule, and cost goals for prototype or production solutions
Participates as a member of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
Provides guidance and mentoring to less experienced staff members

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Verification Engineer II

Verifies, analyzes, develops, modifies and evaluates VLSI/ASIC components and ha...

Location

United States , Roseville

Salary:

89400.00 - 206500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
0-4 years of experience in VLSI/ASIC design, verification or implementation
Experience or understanding of electrical engineering fundamentals, VLSI/ASIC principles, digital logic, and computer architecture
Experience with industry standard verification tools such as System Verilog (SV), UVM, Specman, etc.
Ability to apply analytical and problem solving skills
Hands-on experience in designing VLSI/ASIC components, integrated circuitry, architectures and developing algorithms
Knowledge of a programming and scripting, hardware description language, electronic design automation (EDA), and/or FPGA tools
Coursework in VLSI/ASIC design or VLSI/ASIC concepts
Good written and verbal communication skills
mastery in English and local language

Job Responsibility

Verifies portions of computer/server architecture and algorithms based on established VLSI/ASIC engineering principles and in accordance with provided specifications and requirements
Collaborates and communicates with management regarding design status, project progress, and issue resolution
Verifies, simulates, and tests VLSI/ASIC circuits
Ensures the VLSI/ASIC designs meet quality, schedule, and cost goals for prototype or production solutions
Participates as a member of project team of other VLSI/ASIC engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI/ASIC prototypes and products
Provides guidance and mentoring to less experienced staff members

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

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Asic verification manager

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