Asic verification engineer Job at Hewlett Packard Enterprise (Sunnyvale)

Asic Verification Engineer

Develop and maintain ASIC verification environments using SystemVerilog and UVM ...

Location

India , Bengaluru

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field (BSEE/MSEE)
3+ years of experience in ASIC/SoC verification
Strong expertise in SystemVerilog-based ASIC verification
Hands-on experience with UVM, OVM, or VMM verification methodologies
Knowledge of constrained-random verification techniques
Experience with simulation and debugging using tools such as VCS or NC/Xcelium
Solid understanding of functional coverage, code coverage, and verification signoff processes
Strong ASIC debugging, problem-solving, and root-cause analysis skills
Scripting experience in Perl, Tcl, Python, and/or Shell scripting

Job Responsibility

Develop and maintain ASIC verification environments using SystemVerilog and UVM methodologies
Architect and implement block-level, subsystem-level, and full-chip verification environments
Create, execute, and deliver comprehensive verification test suites for ASIC designs
Perform functional verification using industry-standard simulators such as VCS and NC/Xcelium
Verify complex ASIC blocks independently and drive them to tape-out signoff
Analyze and close code coverage, functional coverage, and support gate-level simulations (GLS)
Debug and resolve design issues by collaborating closely with RTL designers and software/firmware teams
Enhance verification productivity by developing Perl, Python, Tcl, or Shell scripts for automation and infrastructure improvements
Contribute to the adoption and application of advanced verification methodologies, including constrained-random verification and UVM-based verification flows

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Verification Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

ASIC Verification using System Verilog
Experience in constrained-random verification is a strong plus
Experience with verification methodology like OVM/VMM/UVM
Perl/Tcl scripting is strongly preferred
Experience verifying networking protocols such as Ethernet is desirable
Strong problem solving and ASIC debugging skills
MSEE or BSEE is required with 5 plus of experience

Job Responsibility

Architect and Develop block level verification environments for sub-system and full chip using System Verilog and UVM methodology
Define, architect, code, and deliver verification suites/tests for ASICs that enable faster, denser, feature-rich systems
Verify large ASIC blocks independently and rapidly and sign off them for tape-out with analysis of code coverage, functional coverage and Gate level simulation
Work closely with logic designers to resolve bugs and software developers to assist in software and bring-up development
Develop Perl, Python and/or shell scripts to improve current verification infrastructure/methodology

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Asic Verification Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , Roseville

Salary:

153500.00 - 310500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
6-10 years of experience in VLSI design, verification, or implementation
Experience with scripting languages (Python, PERL, TCL or equivalent)
Experience with software programming languages (C
C++)
Experience with Verilog/System Verilog
Proficient in UVM methodologies
Expert level proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
Expert level analytical and problem solving skills
Expert level knowledge of designing VLSI components, integrated circuitry, architectures and algorithms into VLSI solutions

Job Responsibility

Provide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
Reviews and evaluates designs and project activities for compliance with VLSI technology and development guidelines and standards
provides tangible feedback to improve product quality
Provides VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities
Provides leadership of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence
Participates in and provides input on process for selection of future technical leaders
Drives VLSI innovation and integration of new technologies into projects and activities in the design organization

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Experienced Engineer - ASIC Verification

We are starting a new Silicon R&D center in Bangalore. Join our team as we pione...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

Bachelor’s degree in electrical or computer engineering
5+ years industry experience in ASIC IP verification using SystemVerilog and UVM
Experience in developing creating directed/randomized test cases
Experience in implementing scoreboards, checkers, bus functional models within UVM environments
Experience with AMBA-based designs such as AXI and CHI
Experience with SystemVerilog Assertions
Experience with Cadence or Synopsys verification suites
Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results
Experienced at communicating and meeting expectations within and across teams in an agile environment
High attention to detail and commitment to quality

Job Responsibility

Take part in the verification of designs, whether at the block or subsystem level
Participate in defining and implementing UVM-based test environments
Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans
Develop, run, and debug test cases to ensure design quality
Contribute to the improvement and optimization of verification methodologies
Generate documentation throughout the verification lifecycle
Collaborate closely with other verifiers, designers, and architects
Build competence in the technical domain
Engage in cross-team collaboration to ensure successful project delivery

What we offer

Creative Freedom
Global Impact
Work-Life Balance
Professional Growth
An international work environment with opportunities for professional growth and development
A collaborative and inclusive culture that values diversity and innovation

Experienced Engineer - ASIC Verification

We are starting a new Silicon R&D center in Bangalore. Join our team as we pione...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

Bachelor’s degree in electrical or computer engineering
5+ years industry experience in ASIC IP verification using SystemVerilog and UVM
Experience in developing creating directed/randomized test cases
Experience in implementing scoreboards, checkers, bus functional models within UVM environments
Experience with AMBA-based designs such as AXI and CHI
Experience with SystemVerilog Assertions
Experience with Cadence or Synopsys verification suites
Team-oriented, prioritizing team success within the team, across teams, and across sites over individual results
Experienced at communicating and meeting expectations within and across teams in an agile environment
High attention to detail and commitment to quality

Job Responsibility

Take part in the verification of designs, whether at the block or subsystem level
Participate in defining and implementing UVM-based test environments
Support the creation of Verification Strategies and contribute to the development and execution of Verification Plans
Develop, run, and debug test cases to ensure design quality
Contribute to the improvement and optimization of verification methodologies
Generate documentation throughout the verification lifecycle
Collaborate closely with other verifiers, designers, and architects
Build competence in the technical domain
Engage in cross-team collaboration to ensure successful project delivery

What we offer

Creative Freedom
Global Impact
Work-Life Balance
Professional Growth
An international work environment with opportunities for professional growth and development
A collaborative and inclusive culture that values diversity and innovation

Asic Design Verification Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

Canada , Markham; Ottawa

Salary:

128000.00 - 192000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging RTL code using simulation tools
Expert in the UVM concepts and SystemVerilog language
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced in developing UVM based verification frameworks and testbenches, processes and flows
Comfortable automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, formal verification
Scripting language experience: Perl, Python, Makefile, shell preferred
Exposure to leadership or mentorship is an asset
Prior exposure to networking protocols such as Ethernet, UAL, LLR, CBFC is desired

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

What we offer

Benefits offered are described at AMD benefits at a glance

Fulltime

Senior ASIC Design Verification Engineer

Drive advanced verification using UVM methodology to validate complex ASIC featu...

Location

India , Bengaluru

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

15+ years of experience in ASIC Verification using SystemVerilog
Strong expertise in UVM (preferred), OVM, or VMM methodologies
Experience in constrained-random verification
Hands-on experience with ASIC debugging and problem-solving
Proficiency with simulation tools like VCS / NC-Sim
Strong scripting skills in Perl / Tcl (Python is a plus)
Exposure to networking protocols (e.g., Ethernet) is desirable
Demonstrated technical leadership and ownership mindset
B.E/B.Tech or M.E/M.Tech in Electronics or related field

Job Responsibility

Drive advanced verification using UVM methodology to validate complex ASIC features
Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
Define, design, and execute verification plans and test suites for ASICs
Perform verification using simulation tools (VCS / NC-Sim or equivalent)
Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
Perform functional coverage, code coverage, and gate-level simulations (GLS)
Collaborate with RTL designers for debugging and software teams for bring-up and validation
Enhance verification infrastructure through automation using Perl, Python, or Shell scripting

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Engineer, Design Verification

Meta's Infrastructure Silicon team is seeking a Staff ASIC Design Verification E...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Select Country

Asic verification engineer

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