ASIC Validation Engineer Job at Block (Bay Area)

Engineer III – ASIC Validation & Automation

On behalf of our client, a global technology leader focused on developing innova...

Location

United States , Milpitas

Salary:

50.00 - 55.00 USD / Hour

Tucker Parker Smith Group

Expiration Date

Until further notice

Requirements

B.S. or M.S. in Electrical Engineering, Electronics Engineering, Computer Engineering, or equivalent practical experience
5 years of hands-on experience in ASIC development, validation, or related engineering disciplines
Strong proficiency in automation and scripting, including Python, API integration, and workflow orchestration
Demonstrated expertise with validation frameworks, testing methodologies, and agent development
Strong communication skills with the ability to explain complex technical concepts clearly

Job Responsibility

Translate architectural and design specifications into production-ready agents and implementations
Lead ASIC testing and validation efforts across multiple projects and engineering sites
Execute and manage validation workflows, automation, and framework development
Partner closely with platform, design, and validation teams to offload implementation work and accelerate delivery timelines
Develop and maintain automation solutions using Python, APIs, and workflow orchestration tools
Identify, debug, and resolve complex system-level issues to ensure high reliability and performance
Contribute to best practices, documentation, and continuous improvement initiatives

ASIC Engineer, Infra Silicon Pre/Post Silicon Validation

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Technologist, ASIC Development Engineering (ASIC SOC Validation)

We are looking for a Technologist (ASIC validation engineer) to work with our ne...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BS/MS degree in Computer Engineering, Electrical Engineering, Computer Science or related field
12 – 17 years of experience on validation and debug
Experience coding in C for SSD embedded system, Python for test automation is a plus
SSD firmware/validation experience in areas of: USB, SD, PCIe/NVMe, NAND and related areas
Experience with lab debugging tools (debugger, logic analyzer, scope)
Good Knowledge in any of the storage protocol - eMMC/USB/NVMe protocol
Good Knowledge in any of the Electrical validation of the storage protocol - eMMC/USB/SD/SDIO/PCIE
Good Knowledge and hands on experience in scripting in C, Python language
Good Knowledge and deep hands on experience in Failure Analysis to understand the Test and FW/Memory features
Good knowledge in Test application development and performance measurement tool, etc.

Job Responsibility

Validation of DDR, PCIe/SD memory product with Host platforms from different OEM/Chipset vendors
Failure Analysis of the issues to root cause whether it is the test issue or product issue
Understand the architecture and design. Come up with validation plan and execute to completion
Understanding the test scenarios and converting them into test cases
Develop Validation firmware using C/C++ in multiple environments using latest standards: FPGA, Simulator, for flash products
perform tasks including SOC bring-up
features validation
ASIC and storage drive debugging
Compliance and interoperability procedures

Fulltime

New

Ip Post-Silicon Validation Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great pro...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Bachelor's or master’s degree majoring in EE, CS or related field
Experience in digital logic design/verification/post-silicon validation
Extensive experience with ASIC debug techniques and methodologies
Knowledge of physical and protocol levels of common high-speed interfaces such as PCIe/CXL/UALINK is an asset
Experience with board/platform-level debug, including clock/power delivery, sequencing, analysis, and optimization
Strong scripting skills (eg. Ruby, Python)
Extensive experience with common lab equipment, including protocol/logic analyzers, oscilloscopes, etc.
In-depth knowledge of PC architectures/PCIe protocol is an asset
Must have excellent written and verbal communication skills
Must excel in a dynamic team working environment

Job Responsibility

Driving the planning, validation, and debug of various hardware IP for forthcoming AMD APU, CPU, Compute and Discrete Graphics SOC programs
Defining, documenting, executing and reporting the overall functional test plan and validation strategy for a set of AMD IP’s
Driving technical innovation to enhance AMD's capabilities in IP validation, including tools and scripts/automation development, technical and procedural methodology enhancement, and various internal and cross-functional technical initiatives
Debugging IP issues found during pre-silicon, bring-up, system validation, and production phases of the SOC programs
Engaging on pre-silicon ‘shift left’ activities with cross-functional teams such as Design Verification (DV), Diagnostics, Emulation and other software/hardware modeling frameworks to ensure readiness for first silicon arrival, enablement of IP functionality, and debug of critical features
Leading collaborative technical discussions to drive resolution of technical issues and roll out technical initiatives
Developing knowledge of system architecture/debug and other internal IP’s
Supporting issues on customer platforms as requested by customer support teams

Fulltime

Senior Engineer - ASIC Backend Synthesis

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an P...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

8+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl
Python scripting a strong plus
At least one tape-out on 7nm or below
B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts

Job Responsibility

Physical-Aware Synthesis (PAS)
Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing
Collaborate with P&R engineers on DEF/floorplan hand-off
iterate on netlist quality to reduce downstream ECO effort
Perform flat and hierarchical synthesis for large designs
manage partitioning and interface timing budgets
Perform formal or equivalence check on the netlist at block or top level
QoR & Optimization
Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners

Fulltime

Silicon System Validation Engineer

Meta's Silicon Engineers are at the forefront of innovation, driving the design ...

Location

Taiwan , Taipei

Salary:

Not provided

Principal Engineer, ASIC Development Engineering (Frontend Architect - AI Storage Solutions)

In this Frontend Architect position, you will develop AI Storage Solutions based...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors or Masters or PhD in Computer/Electrical Engineering with 8+ years of hands-on Architecture experience authoring specifications
Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines, or UCIe or CXL or UAL
Strong IO subsystem microarchitecture, technical, and working knowledge of the PCIe/UCIe protocol specifications
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU
Good understanding of computer/graphics architecture, ML, LLM
Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech)
Deep experience optimizing large-scale ML systems, GPU architectures
Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering
Multi-disciplinary experience, including familiarity with Firmware and ASIC design
Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations

Job Responsibility

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over UCIe, PCIe, UAL or CXL
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase
Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap
LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products
Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth

Fulltime

Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design)

Principal Engineer will contribute to the design and development of IO and high‑...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering
9+ years of hands-on experience in High‑Speed I/O design
Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis
Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators
Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes
Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies
Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges
Highly analytical mindset with the ability to work effectively in multidisciplinary teams
Creative, innovative thinker with strong personal ownership and attention to detail
Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach

Job Responsibility

Contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes
Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers
Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule
Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality
Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation
Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence
Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices

Fulltime

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ASIC Validation Engineer

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