Asic Top Level Verification-Formal Connectivity Verification Job at Ericsson (Bangalore)

Job Description

Join our new ASIC top level verification team. We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.

Job Responsibility

Experience using tools like Jasper of VC Formal for connectivity/integration verification of large ASICs
SoC level testcase development with possibilities to specialize in special areas related to traffic on external interfaces and/or ASIC internal functionality involving DSPs, MCUs, CPU cores, ARM infrastructure, switches, security, SerDes, DDR and other types of external memory and much more
Preparing and setting up designs to run in Hardware Emulators, and update and maintain existing emulator platforms
Participate in defining/documenting verification strategies for the parts of the ASIC assigned to you as a verifier
As input you have documents and information from interaction with various type of stakeholders
Participate in specification and development of software driven tests written in C
Debug RTL designs with help of EDA simulation tools and SW debuggers
But also debug failing test cases using the SystemC/TLM platform or using the hardware emulator, depending on the situation
Beside RTL simulations you will debug failing test cases running on any of our other run-platforms, SystemC/TLM simulation, Hardware emulation and on Silicon mounted on boards in the lab
In case you lack experience of some platform you are expected to develop skills for such tasks
Contribute to keeping tests clean in the CI regression running on our four platforms

Requirements

Solid C programming skills targeting ASICs or other type of embedded software programming
Solid skills in RTL debugging issues in simulations of SystemVerilog or VHDL designs
Desired: Using SW debuggers, waveforms windows etc. for HW/SW co-debugging of C-code running in the ASIC
Experience of multi core designs is a plus
GLS
Coresight and other JTAG TAP related features
Compiling designs for HW emulation
Formal connectivity verification
High speed interfaces like Ethernet, PCIe, CPRI
ARM CPUs/cores, SMMU
AMBA interconnect, preferably using Cadence STG or IWB
Open, inclusive mindset
Collaborative approach
Strong drive for innovation
Clear communication skills

Nice to have

Experience of multi core designs is a plus
GLS
Coresight and other JTAG TAP related features
Compiling designs for HW emulation
Formal connectivity verification
High speed interfaces like Ethernet, PCIe, CPRI
ARM CPUs/cores, SMMU
AMBA interconnect, preferably using Cadence STG or IWB

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Asic Top Level Verification-Formal Connectivity Verification

Job Description

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Asic Top Level Verification-Formal Connectivity Verification

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