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Join our new ASIC top level verification team. We specialize in the top-level verification of cutting-edge ASICs that power complex high-performance systems. Our designs are either monolithic ASICs or integrated multi-chip-modules holding several hundreds of processor cores, DSPs as well as ARM cores, tailored hardware accelerator IPs and many high-speed interfaces, including Ethernet, CPRI, and PCIe. As an ASIC Top-Level Verification Engineer, you'll be part of a team tackling some of the most challenging verification tasks in the industry, ensuring that our ASICs meet our high standards for performance, functionality, and security. You will play an important role in the team developing environments and/or tests run in SystemC/TLM simulation, RTL environments, hardware emulation, and eventually on Silicon.
Job Responsibility:
RTL debugging with using Waveform debugging tools from one of the three largest EDA vendors
Development of C SW targeting embedded system, using SW debuggers for debugging
Updating testbenches, like adding VIPs
Requirements:
Experience in using Cadence tools, STG/SPA or IWB and solid experience in AMBA protocols
Expertise with UVM-based environments along with exposure to performance verification and traffic modelling (QoS, bandwidth measurements). Additionally experience with large-scale integration is needed to understand the SoC complexities and dependencies
RTL debugging with experience using Waveform debugging tools from one of the three largest EDA vendors
Development of C SW targeting embedded system, using SW debuggers for debugging
Updating testbenches, like adding VIPs
Nice to have:
Basic understanding of UPF and even better with experience from running low power simulations using UPF