CrawlJobs Logo

Asic Rtl Design Engineer

ericsson.com Logo

Ericsson

Location Icon

Location:
United States , Austin

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

Not provided
Save Job
Save Icon
Apply Position

Job Responsibility:

  • Write and verify RTL — clean, purposeful, production-bound code
  • Take designs from specification all the way to silicon CMOS circuitry
  • Analyze and optimize circuits on advanced process nodes
  • Wield state-of-the-art EDA tools to design and verify complex ASICs
  • Partner with engineers across disciplines on cross-functional initiatives
  • Collaborate with the backend team to close on synthesis, area, and timing

Requirements:

  • BS in Electrical or Computer Engineering
  • Several years of hands-on, in industry RTL design experience at block and/or top level
  • Solid foundation in digital logic design
  • Strong command of C/C++, TCL, and/or Python
  • Proficiency in SystemVerilog, Verilog, or VHDL
  • Deep understanding of clock domain crossing (CDC) and static timing analysis (STA)
  • Hands-on experience with RTL linting and CDC tools — Synopsys SpyGlass and its peers

Nice to have:

  • Experience with AMBA interfaces — APB, AXI, ACE-Lite, CHI
  • Background in computer architecture or VLSI systems
  • IP knowledge across SerDes, PCIe, ARM subsystems, DSPs, accelerators, or Ethernet
  • Experience with EDA toolchains from Cadence, Mentor, or Synopsys
  • Comfort with Git and Linux environments
What we offer:
  • Annual bonus opportunity
  • Choice of three medical plan options
  • Dental plan option
  • Company credits for medical and dental premiums
  • 401(K) Plan with automatic 3% company contribution and matching contributions
  • Basic life insurance and basic accidental death and dismemberment coverage
  • Short-term and long-term disability coverage
  • Stock Purchase Plan
  • Minimum of 15 days of accrued vacation
  • Up to 3 personal days per year
  • 11 annual holidays
  • 8 hours of volunteer time
  • 80 hours of sick time annually
  • Up to 16 weeks of paid maternity leave
  • 6 weeks of parental or adoption leave
  • Financial wellness programs
  • Educational assistance
  • Matching gifts
  • Recognition programs

Additional Information:

Job Posted:
May 04, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
Icon
Ericsson - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Asic Rtl Design Engineer

ASIC Design Engineer

Join our dynamic ASIC design team at HPE Aruba Networking, where we’re building ...
Location
Location
United States , Roseville
Salary
Salary:
130500.00 - 300000.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent
  • 6–10 years of experience in VLSI design, verification, or implementation
  • Deep understanding of digital logic, computer architecture, and VLSI fundamentals
  • Proficiency in RTL design (Verilog/SystemVerilog), scripting (Python/TCL), and EDA tools (Synopsys, Cadence, etc.)
  • Strong analytical and problem-solving skills
  • Excellent verbal and written communication skills
  • Experience working in cross-functional or global teams
Job Responsibility
Job Responsibility
  • Lead project teams of internal and outsourced engineers through all stages of VLSI design—from architecture and RTL to validation and physical implementation
  • Drive architecture and logic design decisions, ensuring alignment with performance, power, and area goals
  • Review and evaluate designs for compliance with internal standards and industry best practices
  • Collaborate across functions to integrate VLSI components into broader system platforms
  • Provide technical leadership and mentorship to junior engineers
  • Champion innovation by integrating new technologies and methodologies into our design flows
  • Contribute to the selection and development of future technical leaders
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...
Location
Location
United States , San Jose
Salary
Salary:
148000.00 - 340500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS degree in electrical engineering
  • computer engineering
  • or a related field with 7+ years of experience in block or full-chip physical design
  • Deep design experience in large SoC designs
  • including IP integration
  • padring design
  • bump planning
  • and RDL routing strategy
  • Extensive knowledge and practices in Physical Design
  • including physically aware synthesis
Job Responsibility
Job Responsibility
  • Implement physical design at the large SoC chip level from RTL to GDSII
  • create a design database ready for manufacturing
  • Interact with IP vendors to understand IP integration requirements and integrate all blocks
  • IPs
  • and sub-chips at a large SoC level
  • Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
  • Build full chip floorplan
  • including pads/ports/bump placement
  • block placement and optimization
  • block pins placement and alignment
What we offer
What we offer
  • Comprehensive suite of benefits that supports physical
  • financial and emotional wellbeing
  • Personal and professional development programs
  • Unconditional inclusion and flexibility to manage work and personal needs
  • Fulltime
Read More
Arrow Right

Asic digital design engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Ability to get a security clearance
  • Solid technical understanding of FPGA or ASIC product development
  • Experience with SystemVerilog, VHDL, and Test-Driven Development principles
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Refine and improve the microarchitecture of Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Use high-quality design methods and processes to achieve excellent results
  • Work with other top-notch ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

Senior/Principal ASIC Digital Design Engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate, implement, and verify RTL code for complex ASICs
  • Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Lead design reviews and provide mentorship to junior engineers
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate and develop RTL code for complex ASICs
  • Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
  • 8+ years of experience in ASIC development, with a proven track record of leading complex project
  • Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
  • Strong digital design development and execution skills , solving bugs
  • Experience in grooming team of 1-4 engineers, interacting with many team
  • Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
  • Hands-on experience with industry-standard EDA tools and design flows
  • Deep knowledge on PCIe, axi , DMA, AHB interfaces
  • Expertise in high-performance and low-power design techniques
  • Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly
Job Responsibility
Job Responsibility
  • Design and implements IPs and subsystems
  • Dealing the best of class IPs for all SanDisk products
  • Fulltime
Read More
Arrow Right

ASIC Digital Design Engineering Lead

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Team leadership experience
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
Job Responsibility
Job Responsibility
  • Lead a team of digital design engineers to create a security system on a chip
  • Collaborate with team members and across teams to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right