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Ericsson · IT - Software Development

Asic Rtl Design Engineer

United States, Austin · Job Posted May 04, 2026

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Job Responsibility

Write and verify RTL — clean, purposeful, production-bound code
Take designs from specification all the way to silicon CMOS circuitry
Analyze and optimize circuits on advanced process nodes
Wield state-of-the-art EDA tools to design and verify complex ASICs
Partner with engineers across disciplines on cross-functional initiatives
Collaborate with the backend team to close on synthesis, area, and timing

Requirements

BS in Electrical or Computer Engineering
Several years of hands-on, in industry RTL design experience at block and/or top level
Solid foundation in digital logic design
Strong command of C/C++, TCL, and/or Python
Proficiency in SystemVerilog, Verilog, or VHDL
Deep understanding of clock domain crossing (CDC) and static timing analysis (STA)
Hands-on experience with RTL linting and CDC tools — Synopsys SpyGlass and its peers

Nice to have

Experience with AMBA interfaces — APB, AXI, ACE-Lite, CHI
Background in computer architecture or VLSI systems
IP knowledge across SerDes, PCIe, ARM subsystems, DSPs, accelerators, or Ethernet
Experience with EDA toolchains from Cadence, Mentor, or Synopsys
Comfort with Git and Linux environments

What we offer

Annual bonus opportunity
Choice of three medical plan options
Dental plan option
Company credits for medical and dental premiums
401(K) Plan with automatic 3% company contribution and matching contributions
Basic life insurance and basic accidental death and dismemberment coverage
Short-term and long-term disability coverage
Stock Purchase Plan
Minimum of 15 days of accrued vacation
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time
80 hours of sick time annually
Up to 16 weeks of paid maternity leave
6 weeks of parental or adoption leave
Financial wellness programs
Educational assistance
Matching gifts
Recognition programs

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Asic Rtl Design Engineer

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