ASIC Principal Design Engineer Job at Hewlett Packard Enterprise (Bangalore)

Principal ASIC Design Verification Engineer

As a Design Verification engineer on the ASIC team, you will ensure that the ASI...

Location

United States , Santa Clara

Salary:

173600.00 - 280700.00 USD / Year

Palo Alto Networks

Expiration Date

Until further notice

Requirements

BS in EE, CE, or CS required or equivalent military experience required
MSEE preferred
Minimum 5 years experience in ASIC design verification
Demonstrated success in taking multiple ASIC products from concept to mass production
Expertise in SystemVerilog and UVM
Technical strength in the following areas is required: Defining test plans, including comprehensive adversarial testing
Developing rich functional coverage models
Creating powerful and scalable test benches
Implementing sophisticated self-checking infrastructure with reference models and scoreboards
Developing reusable constrained-random tests

Job Responsibility

Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
Develop flows, methodologies, and infrastructure for emulation
Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
Define new tools and methodologies to continuously improve quality and velocity
Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification

Fulltime

ASIC Digital Design Principal Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Bengaluru

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or related field
Minimum 6 years of experience in bare metal firmware development and silicon testing
Strong understanding of digital design (RTL) and mixed-signal integration principles
Experience with structured firmware development, verification, and documentation processes
Proficiency in project execution, from initial specification through to final testing and validation
Knowledge of SerDes standards and scripting (Shell/Python) is a strong advantage

Job Responsibility

Designing, developing, and testing bare metal firmware for advanced mixed-signal ASICs, with a focus on high-speed SerDes products
Collaborating with analog and digital teams to define specifications and integration requirements for IP blocks and system-on-chip (SoC) solutions
Executing structured firmware development processes, including verification and thorough documentation of design flows
Performing functional and performance tests on prototype test-chips to ensure robust operation and compliance with design specifications
Supporting customer teams by providing technical expertise, troubleshooting, and guidance throughout the product lifecycle
Contributing to project planning, tracking milestones, and ensuring timely delivery of high-quality deliverables
Engaging in continuous learning to stay abreast of industry advancements in SerDes standards, scripting, and digital design methodologies

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away in addition to company holidays, we have ETO and FTO Programs
Family Support maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

Fulltime

Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design)

Principal Engineer will contribute to the design and development of IO and high‑...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering
9+ years of hands-on experience in High‑Speed I/O design
Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis
Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators
Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes
Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies
Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges
Highly analytical mindset with the ability to work effectively in multidisciplinary teams
Creative, innovative thinker with strong personal ownership and attention to detail
Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach

Job Responsibility

Contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes
Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers
Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule
Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality
Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation
Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence
Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices

Fulltime

Principal Engineer, ASIC Development Engineering (Frontend Architect - AI Storage Solutions)

In this Frontend Architect position, you will develop AI Storage Solutions based...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors or Masters or PhD in Computer/Electrical Engineering with 8+ years of hands-on Architecture experience authoring specifications
Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines, or UCIe or CXL or UAL
Strong IO subsystem microarchitecture, technical, and working knowledge of the PCIe/UCIe protocol specifications
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU
Good understanding of computer/graphics architecture, ML, LLM
Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech)
Deep experience optimizing large-scale ML systems, GPU architectures
Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering
Multi-disciplinary experience, including familiarity with Firmware and ASIC design
Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations

Job Responsibility

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over UCIe, PCIe, UAL or CXL
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase
Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap
LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products
Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth

Fulltime

Principal Engineer, ASIC Development Engineering (PD Methodology & CAD Flow)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...

Location

India , Hyderabad

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
M.Tech in VLSI Design or a related field (or equivalent industry experience)
Proficiency in scripting and automation using TCL, Perl, and/or Python
Experience working in multi-project, high-complexity environments with tight schedules

Job Responsibility

Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges

Fulltime

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug
5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic

Job Responsibility

Part of the design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

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ASIC Principal Design Engineer

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