Asic Physical Design Engineer Job at Hewlett Packard Enterprise (San Jose)

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

Fulltime

ASIC Engineer, Physical Design

Meta is hiring ASIC Physical Design Engineers within our Infrastructure organiza...

Location

United States , Sunnyvale

Salary:

146000.00 - 209000.00 USD / Year

Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)

We are seeking a highly skilled and experienced Senior Engineer for our PNR func...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Place and Route Domain
Proven track record of successfully executing PNR
In-depth knowledge of PNR tools (e.g., Synopsys Fusion Compiler, Cadence Innovus) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Subsystem/block level ownership of Floorplanning, place and route flow for low power, high performance designs, debug of timing/power/area issues, clock tree analysis and assisting full chip timing convergence and timing closure
Collaborate with cross-function teams, including design, DFT to streamline PNR process
Drive IP integration strategies that ensure quality ASICs and avoid schedule surprises
Conduct thorough design and timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design convergence
Stay abreast of industry trends and emerging technologies in PNR and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed analysis, reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the PNR team

Fulltime

Sr Physical Design Engineer

This is an on-site, hybrid opportunity. This is not a remote work opportunity. E...

Location

United States , Austin

Salary:

162000.00 - 243000.00 USD / Year

Ericsson

Expiration Date

Until further notice

Requirements

10+ years of physical design experience and minimum of a BS EE/CE
Expert in one or many of these areas – Methods to improve PPA, RTL checks and Synthesis, STA Constraints, DFT clocking architecture, Physical design of high speed interface IPs
Knowledge of System Verilog or VHDL
Accomplished at problem resolution and execution per project plan/needs
Prior experience in a Senior or Lead Engineer role, including direct responsibility for guiding and mentoring junior team members and setting technical direction
Highly team oriented

Job Responsibility

Be an empowered designer tasked with improving PPA of Ericsson ASICs
Evaluate feasibility of architectural features through back end implementation
Partner with front end design teams to address timing, power and congestion challenges
Deliver a synthesized netlist to ASIC BE vendor, and collaborate with vendor to address physical design tradeoffs
Work with DFT and architecture teams to develop timing constraints
Provide technical leadership and direction for junior members of the team
Participate in defining flows, methods and drive continuous improvement

What we offer

Annual bonus
Choice of three medical plan options and a dental plan option
401(k) Plan with automatic 3% company contribution and matching
Basic life insurance and basic accidental death and dismemberment coverage
Short-term and long-term disability coverage
Stock Purchase Plan
15 days of accrued vacation per year
Up to 3 personal days per year
11 annual holidays
8 hours of volunteer time

Fulltime

ASIC Design Engineer

This role has been designed as ‘Onsite’ with an expectation that you will primar...

Location

United States , Sunnyvale

Salary:

120000.00 - 243000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 4+ years of relevant experience
Strong analytical/problem solving skills
Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus
Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired
Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired
Excellent written and verbal communications skills are good to have
Knowledge of Perl/Python is a plus
Experience with AI agentic tools is a plus

Job Responsibility

Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target
Work with the Verification team to make sure your block is fully validated
Provide mentoring/guidance to new college-grad engineers and interns

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Asic Design Engineer Iv

The successful candidate is considered an emerging authority, who applies extens...

Location

United States , Home

Salary:

101326.82 - 243486.84 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor degree in Hardware or Electrical Engineering (EE) with 8-10 years of experience, Masters degree in Hardware or Electrical Engineering (EE) with 6-8 years of experience or a PhD in Hardware or Electrical Engineering (EE) with 3-5 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Perform packaging and an evaluation board for the physical chip
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

ASIC Design Engineer III

Location

United States , Home, New York

Salary:

82437.89 - 198097.02 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Packaging and an evaluation board for the physical chip must also be performed
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

Principal Physical Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
Develop and implement methodologies and strategies to improve physical design efficiency and performance
Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
Implementation of functional ECO with least physical design impact
Design and implement the global clocking scheme at SOC and sub chip levels
Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers

Fulltime

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Asic Physical Design Engineer

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