Asic Physical Design Engineer, Hewlett Packard Enterprise

Hewlett Packard Enterprise

Location:
United States, San Jose

Category:
-

Contract Type:
Employment contract

Salary:

148000.00 - 340500.00 USD / Year

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Job Description:

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware systems. Determines architecture and logic design, design verification through software developed for component and system simulation, and builds physical implementations through development of multidimensional designs involving the layout of complex integrated circuits.

Job Responsibility:

Implement physical design at the large SoC chip level from RTL to GDSII
create a design database ready for manufacturing
Interact with IP vendors to understand IP integration requirements and integrate all blocks
IPs
and sub-chips at a large SoC level
Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
Build full chip floorplan
including pads/ports/bump placement
block placement and optimization
block pins placement and alignment
power grid
and RDL design
Develop the chip-level clock network and clock stations in collaboration with clock experts
Budget timing among blocks and sub-chips at the chip level
generating block/chip-level static timing constraints
Arrange
analyze
and optimize feedthrough and repeaters among all blocks/sub-chips at the chip level
Perform block-level place and route
ensuring the design meets timing
area
power constraints
and all sign-off criteria
Generate and implement ECOs to fix timing
signal integrity
EM/IR violations
PV
and complete formal verification
Integrate DFT into physical design
ensuring alignment with overall test strategies and manufacturing requirements
Run Physical Design verification flow at chip/block level
fixing LVS/DRC/ERC/ANT violations
Collaborate closely with architecture
frontend design
DV
and package teams to ensure cohesive design implementation and successful project tapeouts

Requirements:

BS degree in electrical engineering
computer engineering
or a related field with 7+ years of experience in block or full-chip physical design
Deep design experience in large SoC designs
including IP integration
padring design
bump planning
and RDL routing strategy
Extensive knowledge and practices in Physical Design
including physically aware synthesis
floor-planning
place & route
CTS
and repeater/feedthrough
Experience in developing and implementing power-grid and clock network at chip level
Knowledge of basic SoC architecture and HDL languages like Verilog to work with the logic design team for timing fixes
Experience in physical design verification to debug LVS/DRC/ERC/ANT issues at chip/block level
Exposure to 2.5D/3D packaging
High performance and large chip design experience preferred
Exposure to DFT
Proficiency in writing Linux shell scripts in Perl
TCL
and Python
Real chip tapeout experience in 7nm and/or below with a successful signoff track record
Self-motivated with strong problem-solving and debugging skills
Ability to work effectively in a dynamic group environment

Nice to have:

Exposure to 2.5D/3D packaging
High performance and large chip design experience
Exposure to DFT

What we offer:

Comprehensive suite of benefits that supports physical
financial and emotional wellbeing
Personal and professional development programs
Unconditional inclusion and flexibility to manage work and personal needs

Additional Information:

Job Posted:
July 29, 2025

Employment Type:

Fulltime

Work Type:

Hybrid work

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Asic Physical Design Engineer