ASIC Physical Design Engineer Job at Cisco (Maynard)

ASIC Physical Design Engineer

Cisco

Location:
United States of America , Maynard

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

122000.00 - 172100.00 USD / Year

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Job Description:

Join the Cisco Acacia Communications team in developing intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Acacia’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide.

Job Responsibility:

Own and drive RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm)
Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies
Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs
develop automated scripts within STA tools
Implement and manage timing ECO strategies
Collaborate closely with RTL and DFT designers to debug and root-cause physical implementation issues related to design, tools, etc.
Evaluate and implement new timing methodologies
provide creative debugging solutions
Contribute to best practices and drive methodology alignment across projects

Requirements:

Bachelors degree in Computer or Electrical Engineering and 5+ years of related experience, or Masters degree in Computer or Electrical Engineering and 3+ years of related experience
Hands-on experience in ASIC physical design and implementation
Experience with place & route using tools such as Cadence Innovus, Synopsys ICC2, or industry equivalent tools
Experience with industry standard CAD methodologies (Cadence, Synopsys, or Mentor)

Nice to have:

Experience with floor planning & partitioning, formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, EMIR
Experience with Static Timing Analysis including tools such as PrimeTime-DMSA or Tempus
Experience with Scripting using languages such as TCL, Perl, Python, etc.
Synthesis experience including Synopsys DC/FC
Formal Verification experience using tools such Synopsys Formality or Cadence LEC
Experience with Power Integrity including tools such as Apache Redhawk or Voltus
Physical Verification DRC/LVS experience including tools such as Synopsys ICV or Mentor Calibre

What we offer:

medical, dental and vision insurance
a 401(k) plan with a Cisco matching contribution
paid parental leave
short and long-term disability coverage
basic life insurance
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday
paid year-end holiday shutdown
4 paid days off for personal wellness
Non-exempt employees receive 16 days of paid vacation time per full calendar year
Exempt employees participate in Cisco’s flexible vacation time off program
80 hours of sick time off provided on hire date and each January 1st thereafter
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
annual bonuses subject to Cisco’s policies

Additional Information:

Job Posted:
February 18, 2026

Expiration:
February 27, 2026

Employment Type:

Fulltime

Work Type:

On-site work

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