Asic Intern Job at Hewlett Packard Enterprise (Roseville)

ASIC Design Intern

Students pursuing their university degree. Assists in various tasks aligned with...

Location

Costa Rica , Heredia

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Artificial Intelligence knowledge (concepts and projects)
Problem solving
Debugging
Communication, both written and verbal
Ability to interact with both hardware and software teams
Multitasking
HDLs
VLSI and physical design knowledge is a plus

Job Responsibility

Work with RTL level design based on an architecture or microarchitecture specification
Develop infrastructure and Proof of Concept for Artificial Intelligence usage and optimization
Optimization of current methodologies for RTL convergence using AI concepts
RTL and Infrastructure detailed debug
Write documentation and specifications for certain designs
Collaborate with different teams across the organization to make sure Quality of deliverables meets the needs of design teams

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Parttime

Asic verification engineering intern

An exciting internship opportunity to make an immediate contribution to AMD's ne...

Location

Canada , Ottawa

Salary:

65000.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

3rd/4th year Computer Engineering or Computer Science students
Understanding of digital design principles
Understanding of Object Oriented Coding practices
Experience with Systemverilog, C or C++ programming languages
Experience with Python, Perl or other scripting languages is an asset

Job Responsibility

Contribute to the development of advanced Systemverilog-UVM based verification environments and IP components
Write tests, sequences, and testbench components in SystemVerilog and UVM to achieve verification of the design
Learn to employ a Coverage-Driven Verification methodology with Constrained Random Stimulus
Review and contribute to verification plans and design specifications
Contribute to process improvements via automation of tasks and exploring and evaluating new tools and methodologies
Investigate and root cause issues found during the IP development stage

Fulltime

ASIC Emulation Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience with ASIC development cycles, Pre/Post Silicon Validation
6+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

ASIC Engineer, Infra Silicon Pre/Post Silicon Validation

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience with ASIC development cycles, Pre/Post Silicon Validation
8+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

What we offer

bonus
equity
benefits

ASIC Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience with FW Development, ASIC development cycles, Pre/Post Silicon Validation
6+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, validation FW/SW, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

Senior Product Architect – AI Data Center & SONiC Networking

Senior Product Architect – AI Data Center & SONiC Networking. This role has been...

Location

United States , San Jose

Salary:

172000.00 - 349000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

10 plus years of experience in data center networking, AI infrastructure, or high-performance systems
Deep expertise in: SONiC architecture and internals
Large-scale Ethernet fabrics
High-speed SerDes (112G/224G PAM4) and their impact on system performance
Strong understanding of ASIC pipelines, buffering, ECMP behavior, and congestion mechanisms
Proven ability to diagnose cross-layer performance and reliability issues involving software, hardware, and physical-layer interactions
Hands-on experience with RDMA/RoCE, congestion control, and lossless Ethernet at scale
Experience with automation and tooling (Python, Ansible, Terraform) in large-scale environments
Industry certifications (e.g., CCIE, JNCIE, NVIDIA) or equivalent practical experience preferred

Job Responsibility

Architect ultra-low-latency, lossless Ethernet fabrics supporting tens of thousands of GPUs for AI training and inference
Own the end-to-end SONiC platform architecture and fabric strategy, spanning control plane, management plane, data-plane integration, and operations at scale
Define multi-generation fabric and platform strategy across switch ASICs, NICs, SerDes capabilities, cabling, and system constraints, aligned to power, performance, and deployment realities
Own link-level and physical-layer requirements as they impact SONiC performance, including high-speed PAM4 signaling (112G/224G), error handling, and hardware/software interaction
Align SONiC architectures with next-generation GPU, NIC, and switch platforms, ensuring optimal performance across hardware and software boundaries
Define SONiC capabilities for AI and HPC workloads, including: Lossless Ethernet and RoCE
Congestion management, QoS, and ECN
Dynamic and flow-based load balancing
Drive scale, performance, and resiliency targets for SONiC-based fabrics, including fast convergence, hitless upgrades, and failure recovery
Define and enforce system-level validation criteria, including scale testing, fault injection, performance benchmarking, and upgrade scenarios

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Intern

ASIC Post-Si Verification Engineering Intern to join our team in Roseville, CA. ...

Location

United States , Roseville

Salary:

35.00 - 40.25 USD / Hour

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Currently pursuing a Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or a related technical field
At least 3rd Year of engineering courses completed
Basic programming or scripting knowledge (e.g., Verilog, SystemVerilog Python, PERL, TCL, C, C++)
Experience with hardware design
Strong interest in high-tech and a passion for learning
Excellent communication and interpersonal skills
Strong problem-solving and analytical skills
Ability to work within a team environment

Job Responsibility

Working with the HPE Aruba ASIC development team on next generation products
Having a summer project that will be used for/in the development activities of current or future ASIC's
Working with and learning from the senior members of the ASIC / VLSI team
Responsibilities may include RTL/Physical Design, Pre-Silicon verification
Post-Silicon verification
Formal Verification
Script &/or Tool development
schedule breakdowns, document generation, and several other possible duties

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Silicon Physical Design Engineer

Meta’s mission is to give people the power to build community and bring the worl...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in ASIC Physical Design
Understanding of RTL2GDSII flow and design tapeouts in 3nm or below process technologies
Experience with low power implementation, power gating, multiple voltage rails, UPF knowledge
Experience working with EDA tools like Fusion Compiler, ICC2/Innovus, Primetime, RedHawk
Experience with Python, TCL, Perl programming

Job Responsibility

Develop and own physical design implementation of multi-hierarchy low-power ML Hardware design including physical-aware logic synthesis, floorplan, place and route, static timing analysis, IR Drop, EM, and physical verification in advanced technology nodes
Resolve design and flow issues related to physical design, identify potential solutions, and drive execution
Collaborate with ML architects and designers to understand the ML workloads and develop custom physical design methodologies and recipes to optimize the PPA of ML compute datapath design blocks
Work across disciplines, brainstorm big ideas, work in new technology areas, juggle/coordinate multiple initiatives, drive a concept into a prototype and ultimately guide the transition into a high-volume consumer product
Travel both domestically and internationally

What we offer

bonus
equity
benefits

Fulltime

Asic Intern

Hewlett Packard Enterprise

Location:
United States , Roseville

Category:
IT - Software Development

Contract Type:
Employment contract

Salary:

Job Description:

Job Responsibility:

Requirements:

Additional Information:

Job Posted:
August 26, 2025

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Contract Type:Employment contract

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Job Description:

Job Responsibility:

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Job Posted:August 26, 2025

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Location:
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