Asic Implementation Engineer - Static Verification Job at Meta (Sunnyvale)

Asic Engineer, Implementation

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

166000.00 - 198220.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree (or foreign degree equivalent) in Electronics Engineering, Computer Engineering, Computer Science, Analytics, or related field and 3 years of work experience in the job offered or related occupation
Requires 3 years of experience in the following skills: Front End Design Integration
RTL design using Verilog
RTL Physical Synthesis and design optimization for Power, Performance, Area
Knowledge of front-end and back-end ASIC tools
Floor planning for I/O, Hard Macros
Writing Timing Constraints for Block Synthesis, Timing
Using Synthesis Tools (Design Compiler, Genus)
Using Physical Design Tools (Innovus, ICC)
Using Static Timing Tools (Primetime)

Job Responsibility

Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities
Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
Perform RTL Lint and work with the Designers to create waivers
Perform RTL Clock Domain Crossing Analysis and do block level CDC signoff
Perform RTL Reset Domain Crossing Analysis and do block level RDC signoff
Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
Analyze the inter-block timing and come up with IO budgets for the various partition blocks

What we offer

bonus
equity
benefits

New

Asic Engineer, Physical Design

Meta is building custom silicon to power the next generation of infrastructure a...

Location

United States , Sunnyvale, CA

Salary:

178000.00 - 250000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in ASIC physical design, including hands-on ownership of full physical implementation flows from floorplanning through tapeout
8+ years of experience with industry-standard EDA tools for placement, routing, clock tree synthesis, and signoff (e.g., Synopsys IC Compiler, Cadence Innovus, Primetime, Calibre)
Experience with static timing analysis, timing constraint development, and multi-corner multi-mode closure at advanced process nodes (7nm or below)
Experience defining and improving physical design methodologies, flows, and automation scripts at an organizational level
Experience collaborating cross-functionally with RTL design, circuit design, and verification teams to resolve physical implementation challenges

Job Responsibility

Lead physical implementation of complex ASIC blocks or full chips, including floorplanning, placement, clock tree synthesis, routing, and signoff across advanced process nodes
Define and drive physical design methodology, flow development, and best practices across the physical design organization
Perform and own timing closure, including static timing analysis, timing constraint authoring, and multi-corner multi-mode signoff
Drive power integrity analysis and optimization, including IR drop, electromigration, and dynamic power reduction techniques
Collaborate with RTL design and architecture teams to provide physical design feedback on microarchitecture decisions, floorplan feasibility, and design-for-manufacturability
Partner with custom layout and circuit design teams to integrate analog and mixed-signal blocks into the digital physical implementation flow
Develop and maintain physical design scripts, automation flows, and runsets to improve team productivity and implementation quality
Conduct design rule check and layout versus schematic verification, resolving violations in coordination with foundry and design teams
Evaluate and qualify new EDA tools and process design kits, providing technical recommendations to improve physical implementation outcomes
Mentor other engineers on physical design techniques, flow improvements, and signoff methodology across the team

What we offer

bonus
equity
benefits

Fulltime

New

Asic Engineer, Physical Design

Meta's silicon engineering team is building custom infrastructure silicon to pow...

Location

United States , Sunnyvale

Salary:

114000.00 - 172000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of experience in ASIC physical design, including hands-on work with placement, clock tree synthesis, routing, and timing closure
Experience with industry-standard physical design EDA tools such as Synopsys IC Compiler, Cadence Innovus, or equivalent
Experience performing static timing analysis using tools such as Synopsys PrimeTime or equivalent
Experience with physical verification flows including DRC and LVS signoff using Calibre or equivalent tools
Experience scripting in Tcl, Python, or shell to automate physical design tasks and flows

Job Responsibility

Execute physical design tasks including floorplanning, placement, clock tree synthesis, routing, and timing closure for custom ASIC designs
Perform static timing analysis and work to resolve setup and hold violations across design corners and operating conditions
Collaborate with RTL and logic design engineers to ensure design-for-physical-implementation guidelines are met early in the design cycle
Develop and refine physical design scripts and methodologies to improve automation, quality of results, and turnaround time
Conduct power analysis and implement power optimization strategies including clock gating, multi-voltage domain partitioning, and IR drop mitigation
Run and interpret physical verification signoff checks including DRC, LVS, and ERC to ensure design compliance with foundry rules
Partner with package and board engineers to define bump maps, power delivery networks, and IO ring constraints
Contribute to the development and documentation of physical design flows, best practices, and reusable block-level methodologies
Analyze and resolve congestion, signal integrity, and electromigration issues across hierarchical design blocks

What we offer

bonus
equity
benefits

Fulltime

Staff Engineer, ASIC Development Engineering (STA, PNR and Timing)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable

Job Responsibility

Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
A minimum of 5 years of experience in Static Timing Analysis
Proven track record of successfully executing STA
In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus, Constraints Manager) and methodologies
Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
Excellent problem-solving skills and the ability to think strategically and analytically
Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
Ability to prioritize tasks and manage multiple project work simultaneously
A proactive, results-oriented mindset with a passion for innovation and continuous improvement

Job Responsibility

Own Subsystem level STA, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
Work with IP & Design team for Timing constraints Development & Review activities
Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
Prepare and present detailed timing reports and technical documentation to stakeholders
Foster a culture of innovation, collaboration, and continuous improvement within the STA team

Fulltime

ASIC Engineer, Physical Design

Meta is hiring ASIC Physical Design Engineers within our Infrastructure organiza...

Location

United States , Sunnyvale

Salary:

146000.00 - 209000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience in interpersonal, teamwork, communication skills and experience interfacing with cross-functional teams, IP, and EDA vendors
Experience in physical design and timing closure
Experience with large SOC designs (>20M gates) with frequencies over 1GHZ
Experience in floor planning, place & route, power and clock distribution, and timing convergence of high-frequency designs
Experience with EDA tools like DC/Genus, Innovus/ICC2, Primetime, Redhawk/Voltus, or Calibre
Programming/scripting skills: TCL, Python, Perl or Shell
Knowledge of RTL2GDSII flow and design tape-outs in 5nm or below process technologies
Knowledge of geometry/process/device technology implications on physical design

Job Responsibility

Develop and own physical design implementation of multi-hierarchy low-power and high-performance designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical verification in advanced technology nodes
Resolve design and flow issues related to the physical design, identify potential solutions, and drive execution
Deliver physical design of an end-to-end IP or integration of ASIC/SoC design and point out lower power and higher performance trade-offs
Define and implement schemes, including semi-custom placement and routing, to improve performance and power
Work with the RTL design team to understand partition architecture and drive physical aspects early in the design cycle
Interface with the RTL design team to drive design modifications to resolve congestion/timing issues and implement functional ECO’s
Use EDA tool-based programming and scripting techniques to automate and improve throughput and quality
Interact with tool vendors to drive tool fixes and flow improvements. Perform tool evaluations of new vendor tools and functions

What we offer

bonus
equity
benefits

Asic / Physical Design Engineer (Int, Senior and Principal)

Location

Canada , Ottawa

Salary:

Not provided

Myticas Consulting

Expiration Date

Until further notice

Requirements

8+ years in ASIC Physical Design / Backend Implementation (PnR)
End-to-end experience from netlist to GDSII (full physical design flow)
Strong hands-on with Place & Route (floorplan, CTS, routing, optimization)
Proven timing closure expertise (setup/hold, ECO implementation)
Deep experience with Synopsys and/or Cadence tool suites
Advanced node exposure (FinFET, sub-10nm / 7nm / 5nm preferred)
Strong Static Timing Analysis (STA) and timing report analysis
Experience with clock tree synthesis (CTS) and clock optimization
Solid understanding of DRC/LVS and physical verification flows
IR drop / power integrity analysis and optimization experience

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Asic Implementation Engineer - Static Verification

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