Asic/fpga Design Verification Engineer Job at Teradyne (North Reading)

Asic/Fpga Design Verification Engineer

We are the global test and automation specialists, powering next-generation tech...

Location

United States , North Reading

Salary:

98700.00 - 157900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

3+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry-standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion-based verification methodologies
Experience working within CI/CD development flows

Job Responsibility

Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs
discretionary bonus(es) based on financial performance

Fulltime

New

Formal Verification Engineer

The Formal Verification team is dedicated to formal verification. It provides fo...

Location

Canada , Markham

Salary:

155200.00 - 232800.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Combined ASIC/FPGA design and verification experience
Verify complex IPs including I/O virtualization, PCIe Root Complex/End Point, and high-speed inter-chiplet interconnects using advanced formal verification methodologies
Develop and execute formal functional and security verification strategies to ensure industry-leading design quality and coverage
Apply expertise in high-speed I/O protocols, IP verification, and formal verification technologies to validate next-generation semiconductor designs
Drive adoption of cutting-edge formal verification and automation techniques to improve verification efficiency and accelerate closure
Provide technical leadership, mentorship, and methodology guidance across formal verification projects and teams
Demonstrate strong hands-on experience with AI-based formal verification, including AI-assisted property generation, proof optimization, coverage analysis, root-cause debugging, and verification closure
Collaborate closely with architecture, RTL design, DV, and silicon teams from concept through tapeout and post-silicon validation
Strong background in formal property verification (FPV), sequential equivalence checking (SEC/SEQ/SLEC), and/or academic formal methods
Expertise in a formal property language (SVA preferred), abstraction techniques, formal sign-off and commercial formal tools (VC-Formal, JasperGold, Questa Formal, etc.)

Job Responsibility

Collaborating with architects and designers to understand the design intents
Creating and executing formal verification plans for design blocks
Writing and debugging properties to verify the design, analyzing signatures and pushing for the resolution
Optimizing runtime using formal techniques
Collecting and reporting status and progress
Improving formal setups based on feedbacks from reviews, metrics, etc
Leading and coordinating verification activities for a small team
Training and coaching junior engineers
Developing working procedures, flows and infra
Handling complicated formal problems

What we offer

Benefits offered are described: AMD benefits at a glance

Fulltime

Mbist Design Engineer

Join Cisco's ASIC Design for Test (DFT) Team, where innovation, collaboration, a...

Location

Armenia , Yerevan

Salary:

Not provided

Duo Security

Expiration Date

Until further notice

Requirements

Bachelor's or higher degree in Electrical Engineering, Computer Engineering, or a related technical field
2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs
Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor)
Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test
Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement
Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage
Excellent communication skills and experience collaborating within cross-functional engineering teams

Job Responsibility

Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits
Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs
Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements
Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions
Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability
Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results
report on DFT metrics to ensure compliance with company and industry standards

Fulltime

Mbist Design Engineer

Meet the Team Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, c...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field
2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs
Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor)
Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test
Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement
Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage
Excellent communication skills and experience collaborating within cross-functional engineering teams

Job Responsibility

Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits
Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs
Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements
Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions
Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability
Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results
report on DFT metrics to ensure compliance with company and industry standards

Fulltime

Electrical Engineer - Systems

The Scaling team works on the design of our AI supercomputers, doing everything ...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

At least 10 years of industry experience, including experience designing hardware systems for data center applications
experience in designing EE circuit, CPU/GPU/TPU hw system design, board bring up, system design, integration, and system bring up
Master's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience
Have a strong bias toward action, and won’t take no for an answer
Have experience and good knowledge of system design experience in the mechanical and product design areas, from xPUs, board, rack level to data center level
Have a strong intrinsic desire to learn and fill in missing skills
and an equally strong talent for sharing that information clearly and concisely with others
Are comfortable with ambiguity and rapidly changing conditions

Job Responsibility

Work on Machine Learning/AI hardware systems projects to craft the solutions for current and future data center deployments
Worked with hardware team on test vehicle, bring up board design, evaluating end to end system design trade off
Lead EE circuit level design, work with power, thermal, mechanical teams to drive AI hardware system design
Work with product teams to ensure that goals are met with systems and will work with ASIC/FPGA, Software, and Verification teams to ensure proper verification of features
Work with the manufacturing teams to ensure that designs are manufacturable and ready for volume production, and with the field teams to support systems that are deployed in the data center
Gather system requirements, define architecture, execute hardware design, and product validation
Lead the system bring up, validation, NPI, deployment, and sustaining of hardware solutions
Work cross-functionally with Hardware, Software, Mechanical, Thermal, Validation, Manufacturing, and external vendors
Drive system development from concept through production
Lead debug and root cause analysis of deployed systems

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

Group HR Administrator

Support end-to-end administration of new starters, including: Preparing and issu...

Location

United Kingdom , Derby

Salary:

Not provided

360 Resourcing Solutions

Expiration Date

Until further notice

Requirements

Experience in a HR or shared service environment desirable but not essential
Experience of managing high-volume administrative tasks with strong attention to detail
Ability to quickly learn and effectively apply new systems, processes and work flows
Strong organisational skills with the ability to prioritise workload effectively
Excellent written and verbal communication skills
Experience managing shared inboxes and responding to queries professionally
Proficient in Microsoft Office (Word, Excel, Outlook) and HR systems (desirable)
Ability to handle sensitive and confidential information with discretion
Strong teamwork skills with a proactive and supportive approach
High level of accuracy and commitment to maintaining data integrity

Job Responsibility

Support end-to-end administration of new starters, including: Preparing and issuing contracts and offer documentation
Coordinating onboarding and induction processes
Ensuring all pre-employment checks and documentation are completed
Manage leaver processes, including: Processing resignations and updating HR systems
Coordinating exit documentation and final communications
Process contractual changes, ensuring relevant documentation is issued and HR systems are updated
Monitor probation end dates, ensuring reviews are completed, outcomes recorded, and documentation issued
Maintain and update employee records, ensuring accuracy and compliance within HR systems
Manage and monitor the HR shared inbox, including: Responding to queries in a timely and professional manner
Escalating complex queries where required

What we offer

Refer a friend for £1000 bonus which is unlimited
Generous holiday entitlement
Day off for your birthday
Staff Awards
Hotel and airline discounts
Employee Assistance Programme

Fulltime

Transact Techno Functional

We are currently seeking a Transact Techno Functional to join our team in NOIDA,...

Location

India , NOIDA

Salary:

Not provided

NTT DATA

Expiration Date

Until further notice

Requirements

10+ years of experience on T24 development
Expertise in Java, Jbase, SQL and API (IRIS)
Knowledge of T24 R21, TAFJ, AA module and the DFE(Data Feed Extract) would be advantageous
Expert knowledge of T24 standard tools such as Versions, Enquiries, Reporting and Template Programming
Banking and Financial Services knowledge – Commercial Lending
Bachelor’s degree or equivalent combination of education and work experience
Good communications skills with an ability to interact with customers at all levels

Job Responsibility

Application Support - Provide support within team on issues related to T24. Investigating issue, providing solutions, test and apply data and code fixes
Process Analysis – Work closely with T24 Application analysts to design solutions to effectively meet business requirements. Analyze and troubleshoot T24 issues. Support on T24 and interfaces, specifically in the case of technical issues
Assist in design and execution of system tests to a high standard to identify issues before changes are released to UAT
Work closely with product owner or Business SMEs to understand the requirements and also with QA to formulate the test scenarios and cases

Restaurant Team Member

Want to change up your career and join a company where there’s never a dull mome...

Location

United Kingdom , Northampton

Salary:

Not provided

360 Resourcing Solutions

Expiration Date

Until further notice

Requirements

Previous customer service experience within a dynamic, fast paced environment
Excellent communication skills with a strong focus on the customer
Flexibility to work a range of hours (including early mornings, afternoons, evenings and weekends)
Positive team player

Job Responsibility

Welcoming every customer with a smile and being genuinely friendly at all times
Delivering fast, friendly and accurate service to all customers
Attempt to resolve simple customer enquiries and referring difficult customer enquiries to a Manager
Ensure food is prepared and stored and preparation areas are maintained according to Health & Safety and Audit standards
Carry out temperature checks and record as per company process
Complete daily and weekly cleaning schedules as per cleaning chart
Following critical standards for raw and finished product quality, service speed, cleanliness and sanitation
Adhering to restaurant performance standards for crew stations and as per shift manager directions
Being aware of the goals and targets of the restaurant
Maintain operational & kitchen areas to exceed customer cleanliness, comfort & convenience expectations including the restocking of workstations

Fulltime

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Asic/fpga Design Verification Engineer

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