This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification Engineer, preferably with additional experience in FPGA design. The primary focus of this role is FPGA verification, working closely with cross‑functional teams to deliver high‑quality, robust designs.
Job Responsibility
Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader
Requirements
5+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry‑standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion‑based verification methodologies