ASIC/FPGA Design Engineer Job at Teradyne (North Reading)

Asic/Fpga Design Verification Engineer

We are the global test and automation specialists, powering next-generation tech...

Location

United States , North Reading

Salary:

98700.00 - 157900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

3+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry-standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion-based verification methodologies
Experience working within CI/CD development flows

Job Responsibility

Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs
discretionary bonus(es) based on financial performance

Fulltime

Asic/fpga Design Verification Engineer

Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification ...

Location

United States , North Reading

Salary:

123100.00 - 196900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

5+ years of professional experience in digital logic verification or related roles
Experience with Cadence Xcelium or other industry‑standard simulators
Strong experience with System Verilog and Universal Verification Methodology (UVM)
Working knowledge of common IP protocols (e.g., SPI, AXI, DDR)
Experience with RTL design using Verilog HDL
Familiarity with System Verilog assertion‑based verification methodologies
Experience working within CI/CD development flows

Job Responsibility

Review design requirements and specifications
Write and review verification plans
Develop testbench architecture and implementation
Create reference models
Write System Verilog tests and develop UVM environments
perform debug
Collect, merge, and close functional and code coverage
Manage bugs and issues using a tracking tool
Collaborate closely with logic designers
Communicate technical status and risks to the team leader

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Fulltime

Mbist Design Engineer

Meet the Team Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, c...

Location

Armenia , Yerevan

Salary:

Not provided

Cisco

Expiration Date

Until further notice

Requirements

Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field
2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs
Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor)
Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test
Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement
Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage
Excellent communication skills and experience collaborating within cross-functional engineering teams

Job Responsibility

Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits
Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs
Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements
Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions
Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability
Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results
report on DFT metrics to ensure compliance with company and industry standards

Fulltime

New

Sr Manager, Hardware Engineering (NetSec)

The Hardware Engineering Manager will be responsible for overseeing a hardware d...

Location

United States , Santa Clara

Salary:

192900.00 - 312025.00 USD / Year

Palo Alto Networks

Expiration Date

Until further notice

Requirements

Bachelor's degree in Electrical Engineering or Computer Engineering preferred
Minimum of 10 plus years of experience in system-level hardware design
Minimum 5 plus years of experience of people management skills preferred
Proven track record of successfully leading hardware engineering teams and delivering high-quality, complex design solutions
Strong understanding of the overall product development process
Demonstrated success in process-driven engineering and a history of implementing quality-improvement procedures
Solid understanding of product validation testing
Proven ability to identify and leverage emerging AI/ML-driven EDA features or automation scripts to optimize engineering efficiency and quality
Strong proficiency in EDA software
Expertise in DFM (Design for Manufacturing) and DFT (Design for Test) principles

Job Responsibility

Lead, mentor, and manage a team of board design and signal integrity engineers, fostering a culture of technical excellence and quality-first thinking
Instill a quality-focused mindset within the team, emphasizing that quality is a shared responsibility integrated into every stage of the design process
Evaluate, pilot, and integrate AI-based tools and machine learning techniques into the hardware development lifecycle to accelerate design cycles, automate routine tasks, and enhance quality
Establish, document, and enforce procedures and best practices for board design and SI methodologies to ensure repeatable, high-quality outcomes
Drive 'Shift Left' initiatives to identify and mitigate hardware and signal integrity risks during the earliest phases of architectural definition and simulation
Oversee the entire hardware design lifecycle, from concept generation to detailed PCB design, simulation, prototyping, testing, production release, and sustaining
Collaborate with other disciplines within the Hardware Design team including: PCB layout, Mechanical Design, Power Design, and Validation Test
Collaborate with cross-functional teams including ASIC/FPGA, software, operations, and product management to ensure seamless integration and product success
Review and approve hardware designs, ensuring they meet strict technical specifications, quality standards, cost targets, and project timelines
Create and maintain project schedules, resources, and budgets for hardware design activities

What we offer

restricted stock units
bonus

Fulltime

Electrical Engineer - Systems

The Scaling team works on the design of our AI supercomputers, doing everything ...

Location

United States , San Francisco

Salary:

225000.00 - 445000.00 USD / Year

OpenAI

Expiration Date

Until further notice

Requirements

At least 10 years of industry experience, including experience designing hardware systems for data center applications
experience in designing EE circuit, CPU/GPU/TPU hw system design, board bring up, system design, integration, and system bring up
Master's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience
Have a strong bias toward action, and won’t take no for an answer
Have experience and good knowledge of system design experience in the mechanical and product design areas, from xPUs, board, rack level to data center level
Have a strong intrinsic desire to learn and fill in missing skills
and an equally strong talent for sharing that information clearly and concisely with others
Are comfortable with ambiguity and rapidly changing conditions

Job Responsibility

Work on Machine Learning/AI hardware systems projects to craft the solutions for current and future data center deployments
Worked with hardware team on test vehicle, bring up board design, evaluating end to end system design trade off
Lead EE circuit level design, work with power, thermal, mechanical teams to drive AI hardware system design
Work with product teams to ensure that goals are met with systems and will work with ASIC/FPGA, Software, and Verification teams to ensure proper verification of features
Work with the manufacturing teams to ensure that designs are manufacturable and ready for volume production, and with the field teams to support systems that are deployed in the data center
Gather system requirements, define architecture, execute hardware design, and product validation
Lead the system bring up, validation, NPI, deployment, and sustaining of hardware solutions
Work cross-functionally with Hardware, Software, Mechanical, Thermal, Validation, Manufacturing, and external vendors
Drive system development from concept through production
Lead debug and root cause analysis of deployed systems

What we offer

Medical, dental, and vision insurance for you and your family, with employer contributions to Health Savings Accounts
Pre-tax accounts for Health FSA, Dependent Care FSA, and commuter expenses (parking and transit)
401(k) retirement plan with employer match
Paid parental leave (up to 24 weeks for birth parents and 20 weeks for non-birthing parents), plus paid medical and caregiver leave (up to 8 weeks)
Paid time off: flexible PTO for exempt employees and up to 15 days annually for non-exempt employees
13+ paid company holidays, and multiple paid coordinated company office closures throughout the year for focus and recharge, plus paid sick or safe time (1 hour per 30 hours worked, or more, as required by applicable state or local law)
Mental health and wellness support
Employer-paid basic life and disability coverage
Annual learning and development stipend to fuel your professional growth
Daily meals in our offices, and meal delivery credits as eligible

Fulltime

New

Social Worker – Fostering - Family and Friends Team

Are you passionate about working with Family and Friends Carers and improving th...

Location

United Kingdom , Aylesbury

Salary:

40109.00 - 47629.00 GBP / Year

Buckinghamshire Council

Expiration Date

July 20, 2026

Requirements

Social work qualification
Active SWE registration
Completed ASYE
Working knowledge of legislation and guidance which applies to family and friends work
Experience of working in looked after children or with foster carers
Knowledge of research, inquiries and recent studies affecting this sector of service and an ability to monitor its application in practice
Strong written communication skills
Minimum of 2 years post qualifying experience
Experience and competence in working with the courts and providing written and verbal evidence

Job Responsibility

Deliver targeted and specialist social work services in the area of Kinship Care
Clarify eligibility and undertake statutory social work assessments
Promote the safety and well-being of children and young people
Assess and support prospective Family and Friends carers in line with Fostering Regulations and court proceedings
Hold a manageable caseload of SG and Reg24 assessments
Provide carer support
Work within statutory guidelines and fostering regulations
Assist with duty with opportunities to deliver training, run support groups and be involved in the organisation of carer events
Support the development and growth of the service

What we offer

Market premium of £2,750 per annum for Grade 7
Golden Hello payment after one years service (£1,000 for Grade 6, £2,125 for Grade 7)
Competitive salary with a market increment
Annual leave up to 30 days per year
Opportunity to buy further leave
Up to 15 days per year training, learning and development offer
Free parking across all office sites
Relocation packages available
Generous employer pension contribution
Discounts on Cafés, restaurants and shops

Fulltime

New

Spanish Speaking Caregiver

Join Our Team as a Caregiver in Lake Ariel, PA! *Earn Up to $14hr + Extra Cash T...

Location

United States , Lake Ariel

Salary:

14.00 USD / Hour

CareGivers America

Expiration Date

Until further notice

Requirements

Must be willing to work in Lake Ariel
Fluent in English, bilingual English/Spanish preferred
Availability to work Wednesday, Thursday, Saturday, and Sunday 6am-6pm
Reliable transportation required
Must be able to travel up to 25 miles to client locations

Job Responsibility

Bring comfort and companionship to clients in their homes
Help with daily care like bathing, dressing, toileting, and meals
Keep living spaces clean, safe, and welcoming
Offer medication reminders and support healthy routines
Communicate concerns and escalate safety issues as needed
Be a friendly face and a steady presence

What we offer

Paid Orientation
Weekly Pay
Flexible Schedules
Earn up to $375 for referring a friend
Caregiver Rewards Program
Premium Holiday Pay
Paid Time Off + Benefits including medical, dental, vision, and retirement
Free Employee Assistance Program
Discount Perks
Career Growth

New

Early Years Consultant

Join our Early Years Service, where we champion the joy of learning for the youn...

Location

United Kingdom , Aylesbury

Salary:

36317.00 - 37780.00 GBP / Year

Buckinghamshire Council

Expiration Date

July 02, 2026

Requirements

Educated to degree level or minimum three years equivalent experience in a similar managerial role
Excellent knowledge and first-hand experience of planning and delivering the EYFS
Experience of supporting vulnerable children including those with SEND and working with their families
Excellent planning and organisational skills
Excellent interpersonal skills
Proven ability to negotiate, inspire and maintain highly effective working relationships
Skilful communicator with ability to engage and influence customers, partners and stakeholders

Job Responsibility

Support providers to deliver the EYFS
Work with providers to meet the needs of all children including those from vulnerable groups and those with SEND
Ensure providers deliver high quality inclusive education
Offer advice and support to ensure early years practitioners deliver an inclusive Early Years Foundation Stage curriculum and meet the requirements of the SEND Code of Practice 2014 and Equality Act 2010
Provide comprehensive support and advice to providers on safeguarding, child protection and the management of allegations against the workforce, along with sustainability, sufficiency, and finance
Contribute to the work of the Early Years Service, ensuring sufficiency of places
Support the early years sector and childcare sector with high quality training, facilitating networking groups and providing advice and support to a full range of Early Years and Childcare providers

What we offer

Fair and inclusive culture
Health and well-being initiatives including Employee Assistance Programme, Mental Health First Aiders and mindfulness workshops
Unified voice through Employee Representative Group
Ongoing support and opportunity to develop and progress in career
Opportunities to take part in fun activities such as fundraising and social events
Flexible and agile working arrangements
Discounts on various cafes, restaurants, shops
Auto enrolment onto generous Pension Scheme
Opportunity to gain membership to Costco
Discounted gym memberships

Fulltime

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ASIC/FPGA Design Engineer

Job Description

Job Responsibility

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What we offer

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