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Asic Engineering Design Verification Leader

India, Pune · Job Posted June 04, 2026
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Job Description

Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed, capacity, and reliability. Come join us and take part in shaping COG’s ground-breaking optical solutions by designing, developing, and testing some of the most advanced pluggable, and Co-packaged Optics (CPO) being developed in the industry. You will work with Cisco's outstanding Silicon Photonics team. Our team is responsible for driving the development and optimization of optical transceivers & modules (800G,1.6T & beyond) that seamlessly integrate with Cisco's routing, switching, and datacenter platforms, enabling customers to build scalable, high-performance networks that support emerging technologies including AI/ML workloads, and next-generation data center architectures.

Job Responsibility

  • Develop testbench components for Silicon Photonics subsystems
  • Develop functional coverage models, assertions, and debug complex verification issues within a UVM-based framework
  • Run verification at block & chip level with various high-speed IPs integrated like ODSP, D2D IP, SerDes XSR, SerDes PAM4 integrated drivers/TIA, and control functions
  • Prior to tapeout you will run functional scenarios with CPU FW loaded and verify functionality at the CPU sub-system level
  • You may be involved in FPGA verification
  • Post Silicon you will be involved in ATE test plan and test vector generation, ATE testing and release to production

Requirements

  • Bachelor’s or Masters in Electronics Engineering (or equivalent/related)
  • 8-12 years of functional verification experience
  • Strong skills in SystemVerilog, Python, C and UVM methodology
  • Familiarity with UVM phases, configuration mechanisms, factory overrides, and reuse across block, subsystem, and SoC-level verification
  • Good understanding of CPU sub-systems, FPGA, ODSP & integrated transceiver features, SerDes, Ethernet, D2D PHY IP & Protocols
  • Experience with RTL design, simulation tools, (e.g., Synopsys, Cadence, Mentor Graphics) and ASIC design flow
  • You must be a team player and be able to drive decisions quickly with consensus building
  • Strong analytical, problem-solving and debugging skills
  • Strong teamwork, communication, and organizational skills

Nice to have

  • Proven ability to build UVM components (agents, drivers, monitors, scoreboards, sequences) and implement constrained-random and directed test strategies
  • Ability to understand coverage metrics and functional specifications
  • Understand and implement verification scenarios per full chip analog and digital verification test plans
  • Analyse coverage, add scenarios to enhance coverage and debug functional simulations, add corner verification cases and identify and resolve functional bugs
  • FW/C-Coding and verification of CPU sub-systems with FW
  • Must have good knowledge of Python and C. Develop scripts for automated analysis and reports
  • Good understanding of RTL digital design and DFT (Design for Test) principles
  • Excellent organizational, teamwork, and communication skills
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