ASIC Engineer Job at Hewlett Packard Enterprise (Bangalore)

ASIC Engineer

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Austin

Salary:

158956.00 - 198220.00 USD / Year

Asic Engineer

This role involves designing, analyzing, and developing ASIC hardware systems as...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

7+ years of ASIC design experience
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required

Job Responsibility

Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

What we offer

Comprehensive suite of benefits for physical, financial, and emotional wellbeing
Specific programs for career development
Open communications, empowerment, innovation, teamwork, and customer success culture
Pay for performance culture

Fulltime

New

Asic Engineer Ii, Cloud-Scale Machine Learning Acceleration Team

Utility Computing (UC) AWS Utility Computing (UC) provides product innovations -...

Location

United States , Cupertino

Salary:

157300.00 - 212800.00 USD / Year

myGwork - LGBTQ+ Business Community

Expiration Date

Until further notice

Requirements

Bachelor's degree in Electrical Engineering or a related field
5+ years of relevant field experience

Job Responsibility

Design and optimization of hardware in our data centers including AWS Inferentia, our custom designed machine learning inference datacenter server

What we offer

Sign-on payments
Restricted stock units (RSUs)
Health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
401(k) matching
Paid time off
Parental leave

Fulltime

Senior Engineer - ASIC Backend Synthesis

Join Ericsson’s cutting-edge journey to shape the future of 5G networks! As an P...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

8+ years in physical synthesis or logic design implementation
Expert-level use of Fusion Compiler
Strong SDC constraint authoring and management skills
Experience with physical-aware synthesis flows and P&R hand-off
Working knowledge of STA (PrimeTime)
Proficiency in Tcl
Python scripting a strong plus
At least one tape-out on 7nm or below
B.Tech / M.Tech / M.S. in Electronics Engineering, VLSI Design, Computer Engineering, or a related field
Strong foundation in digital logic design, CMOS circuit theory, and standard-cell library concepts

Job Responsibility

Physical-Aware Synthesis (PAS)
Execute physical-aware and floorplan-driven synthesis flows to minimize post-layout timing and congestion surprises
Integrate synthesis with P&R tools for early physical feedback loops — congestion-aware optimization, placement-aware buffering, and pre-CTS timing
Collaborate with P&R engineers on DEF/floorplan hand-off
iterate on netlist quality to reduce downstream ECO effort
Perform flat and hierarchical synthesis for large designs
manage partitioning and interface timing budgets
Perform formal or equivalence check on the netlist at block or top level
QoR & Optimization
Track and report key QoR metrics — timing slack, area, cell count, power — across design iterations and process corners

Fulltime

Engineer - ASIC

We are hiring for our new Silicon R&D center in Bangalore. Join our team as we p...

Location

India , Bangalore

Salary:

Not provided

Ericsson

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in electrical or computer engineering
Knowledge of ASIC IP design and/or verification [0 to 5 years of experience]
Team-oriented, prioritizing team success
High attention to detail and commitment to quality
Strong focus on meeting project deadlines and deliverables
Strong communication skills

Job Responsibility

Take part in the ASIC IP design and/or verification together with other team members
Develop/Improve state of the art designs [RTL] and testbenches
Collaborate closely with other verifiers, designers, and architects
Build competence in the technical domain

What we offer

Competitive compensation and benefits package
Work-life balance
Continuous learning opportunities
Collaborative and innovative work environment
International work environment
Professional growth and career development

Principal Engineer, ASIC Development Engineering (Frontend Architect - AI Storage Solutions)

In this Frontend Architect position, you will develop AI Storage Solutions based...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors or Masters or PhD in Computer/Electrical Engineering with 8+ years of hands-on Architecture experience authoring specifications
Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines, or UCIe or CXL or UAL
Strong IO subsystem microarchitecture, technical, and working knowledge of the PCIe/UCIe protocol specifications
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU
Good understanding of computer/graphics architecture, ML, LLM
Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech)
Deep experience optimizing large-scale ML systems, GPU architectures
Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering
Multi-disciplinary experience, including familiarity with Firmware and ASIC design
Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations

Job Responsibility

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over UCIe, PCIe, UAL or CXL
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase
Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap
LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products
Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth

Fulltime

Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design)

Principal Engineer will contribute to the design and development of IO and high‑...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electronics & Telecommunication or Electrical Engineering
9+ years of hands-on experience in High‑Speed I/O design
Strong hands-on experience in TX/RX design for high-speed memory interfaces such as DDR4, DDR5, and HBM, including comprehensive timing budget analysis
Practical experience with IO standards and IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration circuits, HV‑tolerant and fail‑safe IOs, and crystal oscillators
Expertise in ESD circuit design, including familiarity with ESD guidelines, methodologies, and best practices across multiple process nodes
Proficient with industry‑standard custom design tools such as Cadence Virtuoso, Synopsys Custom Compiler, and SPICE simulators (HSPICE, Spectre, FineSim), including statistical simulation methodologies
Deep understanding of CMOS technologies, including FinFET nodes and awareness of associated DSM (Deep Sub‑Micron) challenges
Highly analytical mindset with the ability to work effectively in multidisciplinary teams
Creative, innovative thinker with strong personal ownership and attention to detail
Strong theoretical foundation complemented by a pragmatic, solution‑oriented approach

Job Responsibility

Contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes
Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers
Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule
Collaborate with layout engineers by providing clear guidance, performing schematic‑layout reviews, and ensuring design robustness and layout quality
Support SOC integration activities, debug integration issues, and participate in post‑tapeout efforts including silicon characterization and performance validation
Provide technical guidance to junior engineers, support their ramp‑up, and contribute to fostering a culture of technical excellence
Contribute ideas for design improvements, propose enhancements to design methodologies, and support the development of efficient flows and best practices

Fulltime

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Austin

Salary:

132198.00 - 162580.00 USD / Year

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ASIC Engineer

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