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This role involves designing, analyzing, and developing ASIC hardware systems as part of a fast-paced team at Hewlett Packard Enterprise. Responsibilities include delivering high-speed ASICs for complex systems, collaborating with verification and physical design teams, and mentoring less experienced engineers. The position is hybrid, requiring 2 days per week at the Bangalore office.
Job Responsibility:
Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
Requirements:
7+ years of ASIC design experience
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required
Nice to have:
Experience designing ASICs for networking protocols (Ethernet, FCoE)
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass
What we offer:
Comprehensive suite of benefits for physical, financial, and emotional wellbeing
Specific programs for career development
Open communications, empowerment, innovation, teamwork, and customer success culture
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