Asic engineer intern, design verification Job at Meta (Bangalore)

ASIC Engineer Intern, Design

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organi...

Location

India , Bangalore

Salary:

Not provided

ASIC Design Engineer

This role has been designed as ‘Onsite’ with an expectation that you will primar...

Location

United States , Sunnyvale

Salary:

120000.00 - 243000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 4+ years of relevant experience
Strong analytical/problem solving skills
Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus
Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired
Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired
Excellent written and verbal communications skills are good to have
Knowledge of Perl/Python is a plus
Experience with AI agentic tools is a plus

Job Responsibility

Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target
Work with the Verification team to make sure your block is fully validated
Provide mentoring/guidance to new college-grad engineers and interns

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Asic Design Engineer Iv

The successful candidate is considered an emerging authority, who applies extens...

Location

United States , Home

Salary:

101326.82 - 243486.84 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor degree in Hardware or Electrical Engineering (EE) with 8-10 years of experience, Masters degree in Hardware or Electrical Engineering (EE) with 6-8 years of experience or a PhD in Hardware or Electrical Engineering (EE) with 3-5 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Perform packaging and an evaluation board for the physical chip
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

ASIC Design Engineer III

Location

United States , Home, New York

Salary:

82437.89 - 198097.02 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Packaging and an evaluation board for the physical chip must also be performed
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

Design Verification Engineer - Internal IP

We are seeking a Design Verification Engineer to join our Internal IP DV team. Y...

Location

United States , San Jose

Salary:

150000.00 - 275000.00 USD / Year

Etched

Expiration Date

Until further notice

Requirements

Proficiency with UVM and SystemVerilog
Strong debugging and problem-solving skills for complex digital designs
Solid knowledge of computer architecture and digital design fundamentals
Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics

Job Responsibility

Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems)
Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks
Debug complex datapath and protocol issues in RTL and testbench environments
Work closely with architects and designers to validate functionality and design intent
Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage
Contribute to reusable DV infrastructure, coverage models, and methodology improvements

What we offer

Medical, dental, and vision packages with generous premium coverage
$500 per month credit for waiving medical benefits
Housing subsidy of $2k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch + dinner in our office

Fulltime

Asic Verification Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

United States , Roseville

Salary:

153500.00 - 310500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer engineering or equivalent
6-10 years of experience in VLSI design, verification, or implementation
Experience with scripting languages (Python, PERL, TCL or equivalent)
Experience with software programming languages (C
C++)
Experience with Verilog/System Verilog
Proficient in UVM methodologies
Expert level proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture
Expert level analytical and problem solving skills
Expert level knowledge of designing VLSI components, integrated circuitry, architectures and algorithms into VLSI solutions

Job Responsibility

Provide technical expertise and leads project teams of Electronic and VLSI engineers and internal and outsourced development partners responsible for all stages of VLSI design and development for complex products, solutions, and platforms, including design, validation, and testing
Reviews and evaluates designs and project activities for compliance with VLSI technology and development guidelines and standards
provides tangible feedback to improve product quality
Provides VLSI-specific and technical expertise along with the overall architecture design and platform leadership to cross-organization projects, programs, and activities
Provides leadership of project team of other VLSI engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for VLSI prototypes and products
Provides guidance and mentoring to less experienced staff members to set an example of VLSI design and development innovation and excellence
Participates in and provides input on process for selection of future technical leaders
Drives VLSI innovation and integration of new technologies into projects and activities in the design organization

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Engineer, Formal Verification

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organ...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Asic Implementation Engineer - Static Verification

Location

United States , Sunnyvale

Salary:

114000.00 - 172000.00 USD / Year

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Asic engineer intern, design verification

Job Description

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Asic engineer intern, design verification

ASIC Engineer Intern, Design

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ASIC Engineer, Formal Verification

Asic Implementation Engineer - Static Verification

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