CrawlJobs Logo

ASIC Engineer, Formal Verification

meta.com Logo

Meta

Location Icon

Location:
United States , Sunnyvale

Category Icon
Category:
IT - Software Development

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

178000.00 - 250000.00 USD / Year
Save Job
Save Icon
Apply Position

Job Description:

Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Formal Verification to build IP and System On Chip (SoC) for data center applications. As a Formal Verification Engineer, you will be part of a team working with the best in the industry, focused on developing innovative ASIC solutions for Meta’s data center applications. You will be developing comprehensive formal testplans and be responsible for complete formal verification sign-off of single or multiple complex blocks. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post-Silicon teams towards creating a first-pass silicon success.

Job Responsibility:

  • Provide technical leadership in Formal Verification
  • Propose, implement and evangelize the Formal Verification Methodology to be used across the group, both at the top level and at the block level
  • Work with Architecture and Design team to come up with formal specification and implementation
  • Define formal verification scope, create formal environment and close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level
  • Build reusable/scalable environments for Formal Verification and deploying the tools
  • Evaluate and recommend EDA solutions for Formal Verification
  • Provide training for internal teams and mentoring engineers related to Formal Verification Technology

Requirements:

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in Design Verification
  • 5+ years of experience in Formal Verification
  • Experience with Formal Verification applications including Datapath, sequential equivalence, Xprop, Clock Gating, connectivity etc
  • Proven understanding of Formal Verification methodologies, complexity reduction techniques and abstraction techniques
  • Proven analytical skills to craft novel solutions to tackle industry-level complex designs
  • Demonstrated experience with effective collaboration with cross functional teams
  • Fluency in hardware description languages, such as SystemVerilog and SVA
  • Proficiency in scripting languages such as Python, Perl, or Tcl
  • Experience with JasperGold or VC-Formal

Nice to have:

  • Experience to quickly understand and interpret specifications and extract design behaviors/properties
  • Experience in formal property verification of complex compute blocks such as DSP, CPU, GPU or HW accelerators
  • Experience with complex SoCs
  • Formal verification experience in clock domain crossing, IP-XACT based register verification and low power
  • Experience with development of fully automated flows from specification to fully verified designs
  • Experience with simulators and waveform debugging tools
What we offer:
  • bonus
  • equity
  • benefits

Additional Information:

Job Posted:
January 23, 2026

Icon
Meta - All Job Offers
Job Link Share:
Copy Link Icon
Facebook Icon Twitter Icon LinkedIn Icon

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for ASIC Engineer, Formal Verification

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate and develop RTL code for complex ASICs
  • Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Staff Silicon Design Engineer

Push Boundaries, Deliver Innovation and Change the World! In this role you will ...
Location
Location
Malaysia , Penang
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong analytical and problem solving skills with a pronounced attention to detail
  • Strong communication, mentoring and leadership skills
  • Skilled at driving team and tasks from start to completion with superior quality
  • Can work well with cross functional teams
  • Good understanding on ASIC/SOC design verification flow with SV/UVM/Formal Verification
  • Good experiences with simulation model creation and testbench build (better with UVM)
  • Good logical thinking and expression
  • Good cooperation cross teams
  • Good verbal and written communication skills in English
  • Bachelors or Masters degree in Computer Engineering/Electrical and Electronics Engineering
Job Responsibility
Job Responsibility
  • Apply current functional verification techniques to perform and improve pre-silicon IP verification quality and product Time to Market for ASIC/SOC design
  • Technically involve in the porting/creation of the DV environment for the new design, block and IP level test plan creation and implementation, coverage analysis, and regression cleanup
  • Work independently on various DV tasks and providing technical guidance to the DV team, or even lead a big DV task inside team or cross team
Read More
Arrow Right

Asic Physical Design Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...
Location
Location
United States , San Jose
Salary
Salary:
148000.00 - 340500.00 USD / Year
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS degree in electrical engineering
  • computer engineering
  • or a related field with 7+ years of experience in block or full-chip physical design
  • Deep design experience in large SoC designs
  • including IP integration
  • padring design
  • bump planning
  • and RDL routing strategy
  • Extensive knowledge and practices in Physical Design
  • including physically aware synthesis
Job Responsibility
Job Responsibility
  • Implement physical design at the large SoC chip level from RTL to GDSII
  • create a design database ready for manufacturing
  • Interact with IP vendors to understand IP integration requirements and integrate all blocks
  • IPs
  • and sub-chips at a large SoC level
  • Collaborate with the packaging team on Microbump/Probe Bump/Bump/Pad placement
  • Build full chip floorplan
  • including pads/ports/bump placement
  • block placement and optimization
  • block pins placement and alignment
What we offer
What we offer
  • Comprehensive suite of benefits that supports physical
  • financial and emotional wellbeing
  • Personal and professional development programs
  • Unconditional inclusion and flexibility to manage work and personal needs
  • Fulltime
Read More
Arrow Right

Senior/Principal ASIC Digital Design Engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

ASIC Digital Design Engineering Lead

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Proven work experience designing and fabricating an ASIC (no exceptions)
  • Ability to get a security clearance
  • Solid technical background with at least 5 years of experience in FPGA or ASIC product development
  • Team leadership experience
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
Job Responsibility
Job Responsibility
  • Lead a team of digital design engineers to create a security system on a chip
  • Collaborate with team members and across teams to explore and clearly identify real problems and solutions
  • Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Define and improve high-quality design methods and processes
  • Mentor and guide other ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

Asic digital design engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...
Location
Location
United States , Boise; Salt Lake City
Salary
Salary:
Not provided
idahoscientific.com Logo
Idaho Scientific
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • US Citizenship (no exceptions)
  • Ability to get a security clearance
  • Solid technical understanding of FPGA or ASIC product development
  • Experience with SystemVerilog, VHDL, and Test-Driven Development principles
  • Ability to communicate clearly in person and in written documentation
  • Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
  • In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
  • Strong analytical and problem solving skills
  • Extreme attention to detail
  • A willingness to roll up one’s sleeves to get the job done
Job Responsibility
Job Responsibility
  • Collaborate with team leaders to explore and clearly identify real problems and solutions
  • Refine and improve the microarchitecture of Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
  • Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
  • Integrate complex systems that instantiate both Idaho Scientific and third party IP
  • Contribute to all aspects of design success from specification to production
  • Apply our state-of-the-art IP to ASIC and FPGA products in the real world
  • Use high-quality design methods and processes to achieve excellent results
  • Work with other top-notch ASIC design engineers
What we offer
What we offer
  • Competitive Pay
  • Flexible Work Schedule
  • Health Benefits and Insurance
  • Retirement fund contributions
  • Profit Sharing
  • Generous Paid Time Off Policy
  • Fulltime
Read More
Arrow Right

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
  • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
  • Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
  • Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
  • Proficiency in scripting languages (e.g., Python, TCL) for automation
  • Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
  • Strong problem-solving skills and the ability to thrive in a dynamic environment
  • Excellent communication and teamwork abilities
Job Responsibility
Job Responsibility
  • Innovate, implement, and verify RTL code for complex ASICs
  • Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
  • Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
  • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
  • Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
  • Lead design reviews and provide mentorship to junior engineers
  • Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
  • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design
  • Fulltime
Read More
Arrow Right

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...
Location
Location
United States , Irvine
Salary
Salary:
Not provided
xcelerium.com Logo
Xcelerium
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5+ years of ASIC and/or physical design flow development experience
  • Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
  • Scripting experience with Python, Tcl, or Perl
  • Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
  • Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
Job Responsibility
Job Responsibility
  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
  • Fulltime
Read More
Arrow Right
Jobs by Category
Art and Entertainment Jobs Banking Jobs Call Center Jobs Construction Jobs Consulting Jobs Customer Service Jobs Education Jobs Energy Jobs Finance Jobs Gastronomy Jobs Health and Beauty Jobs Hospitality and Tourism Jobs Human Resources Jobs Insurance Jobs IT - Administration Jobs IT - Software Development Jobs Legal Jobs Logistics Jobs Manufacturing Jobs Marketing, Digital Marketing, SEO, SEM Jobs Media Jobs Nursing Jobs Office Administration Jobs Pharmacy Jobs Physical Work Jobs Public Relations Jobs Public Sector Jobs Purchasing Jobs Quality Control Jobs Real Estate Jobs Research and Development Jobs Sales Jobs
Job Positions Jobs by Country
United States Jobs United Kingdom Jobs India Jobs Canada Jobs Australia Jobs Germany Jobs Ireland Jobs Poland Jobs
Company
Blog About Us Contact
Follow Us
Facebook
X (Twitter)
LinkedIn
Instagram
CrawlJobs Group
ITFlashcards AllDevBlogs
© 2026 CrawlJobs Ltd. All Rights Reserved
Terms & Conditions Privacy Policy