ASIC Engineer, Emulation Job at Meta (Sunnyvale)

ASIC Emulation Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience with ASIC development cycles, Pre/Post Silicon Validation
6+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

Lead Platform Emulation Engineer

The focus of this role is to plan, build, execute the verification, validation/e...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer/Electronics/Electrical Engineering with 18+ years of experience
Experience with BIOS/OS bring up on full X86 SOC emulation platform
Proficient in IP level ASIC verification, experience working with CPU, GPU, and Memory subsystem
Proficient in debugging firmware and RTL code using simulation tools
Good understanding of PCIe/USB/Ethernet standards
safety concepts/IPs
Must have hands-on experience on Zebu/Palladium/Veloce platform to bring-up SOC
SOC design model build experience
Experienced with Verilog, System Verilog, C, and C++
Experience in writing and debugging testbenches

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Drive Emulation Methodologies, SOC Design Model and Test Architecture for full chip SOC and hybrid models
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed Pre-Silicon Emulation tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test or infra issues
Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
Responsible for running emulator workloads to test new features and debug technical issues using logs, waveform dumps and RTL debug

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Austin

Salary:

132198.00 - 162580.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires a Bachelor’s degree (or foreign equivalent) in Computer Science, Computer Software, Computer Engineering, Electrical and Computer Engineering, Electronics and Telecommunication Engineering, Applied Sciences, Mathematics, Physics, or related field and 1 year of work experience in the job offered or in a computer-related occupation
Requires 1 year of experience in the following: Verilog, System Verilog/UVM methodology or C/C++ based verification
Block/IP/sub-system or SoC level verification based on SystemVerilog UVM/OVM based methodologies
EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Implementing Design Verification infrastructure (Testbench, RAL based register verification, Functional coverage, or Regression setup) and executing the full verification cycle
Industry standard Bus Protocols, such as AMBA AXI, AHB, or APB

Job Responsibility

Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Define and implement IP/SoC verification plans, build verifications test benches to block IP/subsystem/SoC level verification and develop functional tests based Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

149000.00 - 162580.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires a Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Computer Science, Electrical and Computer Engineering, Electronics and Telecommunication Engineering or related field
2 years of work experience in the job offered or related occupation
2 years of experience in Verilog, System Verilog/UVM methodology based verification
2 years of experience in Block/IP/sub-system and/or SoC level verification based on System Verilog UVM based methodologies
2 years of experience in EDA tools and scripting (Python, Shell) used to build tools and flows for verification environments
2 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
2 years of experience in Developing and executing verification test plans, random stimulus, coverage, and assertions
2 years of experience in debugging and root cause failures and tracking verification completion using metrics
2 years of experience working in a CPU or GPU or HW Accelerator verification
2 years of experience in executing a full verification cycle

Job Responsibility

Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Define and implement ASIC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests
Debug, rootcause and resolve functional failures in the design, partnering with the Design team
Collaborate with crossfunctional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

Fulltime

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

186000.00 - 192170.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, followed by 3 years of work experience in the job offered or a computer-related occupation
Requires 3 years of experience in Verilog, System Verilog/UVM methodology based verification
Requires 3 years of experience in Block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM based methodologies
Requires 3 years of experience in EDA tools and scripting (C++ or Python, Shell) used to build tools and flows for verification environments
Requires 3 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
Requires 3 years of experience in Developing and executing verification testplans, random stimulus, coverage
Requires 3 years of experience in Debugging and root cause failures and tracking verification completion using metrics
Requires 3 years of experience in Working in a CPU or GPU or SOC or HW Accelerator verification
Requires 3 years of experience in Executing a full verification cycle

Job Responsibility

Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Define and implement ASIC verification plans, build verifications test benches to block IP/sub-system/SoC level verification and develop functional tests
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organ...

Location

United States , Sunnyvale

Salary:

114000.00 - 172000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Job Responsibility

Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

Fulltime

ASIC Engineer, Infra Silicon Pre/Post Silicon Validation

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience with ASIC development cycles, Pre/Post Silicon Validation
8+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

What we offer

bonus
equity
benefits

ASIC Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
6+ years of experience with FW Development, ASIC development cycles, Pre/Post Silicon Validation
6+ years of experience with troubleshooting, debug and analytics for Silicon products
Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
Experience working with internal and external partners for ASIC and/or systems development
Experience in ASIC Design or Development, Emulation and Post Silicon validation

Job Responsibility

Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
Create/develop validation plan, validation FW/SW, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
Understand production system use cases to improve silicon validation
Provide feedback into next generation architecture and design with insights from the production fleet
Root-cause, resolve and remediate issues with silicon across the product lifecycle
Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

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ASIC Engineer, Emulation

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