CrawlJobs Logo
Meta Logo Meta · IT - Software Development

ASIC Engineer, Design Verification

United States, Sunnyvale 149000.00 - 162580.00 USD / Year · Job Posted March 19, 2026
Apply Position
Job Link Share

Job Description

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology.

Job Responsibility

  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Define and implement ASIC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests
  • Debug, rootcause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with crossfunctional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

Requirements

  • Requires a Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Computer Science, Electrical and Computer Engineering, Electronics and Telecommunication Engineering or related field
  • 2 years of work experience in the job offered or related occupation
  • 2 years of experience in Verilog, System Verilog/UVM methodology based verification
  • 2 years of experience in Block/IP/sub-system and/or SoC level verification based on System Verilog UVM based methodologies
  • 2 years of experience in EDA tools and scripting (Python, Shell) used to build tools and flows for verification environments
  • 2 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
  • 2 years of experience in Developing and executing verification test plans, random stimulus, coverage, and assertions
  • 2 years of experience in debugging and root cause failures and tracking verification completion using metrics
  • 2 years of experience working in a CPU or GPU or HW Accelerator verification
  • 2 years of experience in executing a full verification cycle

What we offer

  • bonus
  • equity
  • benefits
Meta - All Job Offers

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Suggested Tags: Frontend Developer Secretary Talent Manager Salesforce Administrator Data Analyst
Similar Jobs for

ASIC Engineer, Design Verification

8 matching positions

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...
Location
Location
United States , Austin
Salary
Salary:
132198.00 - 162580.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Requires a Bachelor’s degree (or foreign equivalent) in Computer Science, Computer Software, Computer Engineering, Electrical and Computer Engineering, Electronics and Telecommunication Engineering, Applied Sciences, Mathematics, Physics, or related field and 1 year of work experience in the job offered or in a computer-related occupation
  • Requires 1 year of experience in the following: Verilog, System Verilog/UVM methodology or C/C++ based verification
  • Block/IP/sub-system or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
  • Implementing Design Verification infrastructure (Testbench, RAL based register verification, Functional coverage, or Regression setup) and executing the full verification cycle
  • Industry standard Bus Protocols, such as AMBA AXI, AHB, or APB
Job Responsibility
Job Responsibility
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Define and implement IP/SoC verification plans, build verifications test benches to block IP/subsystem/SoC level verification and develop functional tests based Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality
What we offer
What we offer
  • bonus
  • equity
  • benefits
Read More
Arrow Right

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...
Location
Location
United States , Sunnyvale
Salary
Salary:
186000.00 - 192170.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, followed by 3 years of work experience in the job offered or a computer-related occupation
  • Requires 3 years of experience in Verilog, System Verilog/UVM methodology based verification
  • Requires 3 years of experience in Block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM based methodologies
  • Requires 3 years of experience in EDA tools and scripting (C++ or Python, Shell) used to build tools and flows for verification environments
  • Requires 3 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
  • Requires 3 years of experience in Developing and executing verification testplans, random stimulus, coverage
  • Requires 3 years of experience in Debugging and root cause failures and tracking verification completion using metrics
  • Requires 3 years of experience in Working in a CPU or GPU or SOC or HW Accelerator verification
  • Requires 3 years of experience in Executing a full verification cycle
Job Responsibility
Job Responsibility
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Define and implement ASIC verification plans, build verifications test benches to block IP/sub-system/SoC level verification and develop functional tests
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality
What we offer
What we offer
  • bonus
  • equity
  • benefits
Read More
Arrow Right

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organ...
Location
Location
United States , Sunnyvale
Salary
Salary:
114000.00 - 172000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
  • 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
  • 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Job Responsibility
Job Responsibility
  • Define and implement block/IP/System on Chip (SoC) verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
What we offer
What we offer
  • bonus
  • equity
  • benefits
  • Fulltime
Read More
Arrow Right

ASIC Engineer, Design Verification

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organ...
Location
Location
United States , Sunnyvale
Salary
Salary:
146000.00 - 209000.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Job Responsibility
Job Responsibility
  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
What we offer
What we offer
  • bonus
  • equity
  • benefits
Read More
Arrow Right
New

Sr ASIC Design Verification Engineer (NetSec)

As a Design Verification engineer on the ASIC team, you will ensure that the ASI...
Location
Location
United States , Santa Clara
Salary
Salary:
Not provided
paloaltonetworks.com Logo
Palo Alto Networks
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS in EE, CE, or CS required or equivalent military experience required - MSEE preferred
  • Minimum 5 years experience in ASIC design verification
  • Demonstrated success in taking multiple ASIC products from concept to mass production
  • Expertise in SystemVerilog and UVM Technical strength in the following areas is required
  • Defining test plans, including comprehensive adversarial testing
  • Developing rich functional coverage models
  • Creating powerful and scalable test benches Implementing sophisticated self-checking infrastructure with reference models and scoreboards
  • Developing reusable constrained-random tests
  • Debugging failures
  • Closing coverage
Job Responsibility
Job Responsibility
  • Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
  • Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
  • Develop flows, methodologies, and infrastructure for emulation
  • Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
  • Define new tools and methodologies to continuously improve quality and velocity
  • Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification
What we offer
What we offer
  • restricted stock units and a bonus
  • A description of our employee benefits may be found here
  • Fulltime
Read More
Arrow Right

ASIC Design Verification Engineer

Meet the Team: The Common Hardware Group (CHG) delivers the silicon, optics, and...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
Cisco
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s Degree or equivalent experience in EE, CE, or other related field
  • 7+ years of related ASIC design verification experience
  • Proficient in ASIC verification using UVM/System Verilog
  • Proficient in verifying sophisticated blocks, clusters and top level for ASIC
  • Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes
Job Responsibility
Job Responsibility
  • Architect block, cluster and top-level DV environment infrastructure
  • Develop DV infrastructure from scratch
  • Maintain and improve existing DV environments
  • Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
  • Ensure complete verification coverage through implementation and review of code and functional coverage
  • Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
  • Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance
  • Support testing of design in emulation
  • Lead all aspects of and manage the ASIC bring-up process
  • Fulltime
Read More
Arrow Right

ASIC Design Verification Engineer

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platf...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
duo.com Logo
Duo Security
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's Degree or equivalent experience in EE, CE, or other related field
  • 7+ years of related ASIC design verification experience
  • Proficient in ASIC verification using UVM/System Verilog
  • Proficient in verifying sophisticated blocks, clusters and top level for ASIC
  • Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes
Job Responsibility
Job Responsibility
  • Architect block, cluster and top-level DV environment infrastructure
  • Develop DV infrastructure from scratch
  • Maintain and improve existing DV environments
  • Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
  • Ensure complete verification coverage through implementation and review of code and functional coverage
  • Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
  • Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance
  • Support testing of design in emulation
  • Lead all aspects of and manage the ASIC bring-up process
  • Fulltime
Read More
Arrow Right

Senior ASIC Design Verification Engineer

Drive advanced verification using UVM methodology to validate complex ASIC featu...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 15+ years of experience in ASIC Verification using SystemVerilog
  • Strong expertise in UVM (preferred), OVM, or VMM methodologies
  • Experience in constrained-random verification
  • Hands-on experience with ASIC debugging and problem-solving
  • Proficiency with simulation tools like VCS / NC-Sim
  • Strong scripting skills in Perl / Tcl (Python is a plus)
  • Exposure to networking protocols (e.g., Ethernet) is desirable
  • Demonstrated technical leadership and ownership mindset
  • B.E/B.Tech or M.E/M.Tech in Electronics or related field
Job Responsibility
Job Responsibility
  • Drive advanced verification using UVM methodology to validate complex ASIC features
  • Architect and develop block, subsystem, and full-chip verification environments using SystemVerilog and UVM
  • Define, design, and execute verification plans and test suites for ASICs
  • Perform verification using simulation tools (VCS / NC-Sim or equivalent)
  • Own end-to-end verification of large ASIC blocks, including coverage analysis and tape-out sign-off
  • Perform functional coverage, code coverage, and gate-level simulations (GLS)
  • Collaborate with RTL designers for debugging and software teams for bring-up and validation
  • Enhance verification infrastructure through automation using Perl, Python, or Shell scripting
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right