ASIC Engineer, Accelerator Systems Job at Meta (Bangalore)

System Validation Engineer

We’re hiring a Sr. Staff/Staff Systems Engineer at Achronix. If you are a system...

Location

United States , Santa Clara

Salary:

Not provided

Achronix Semiconductor

Expiration Date

Until further notice

Requirements

Expertise with PCIE and/or Ethernet specification protocols
Hands-on in lab environment
Well-versed with lab equipment such as BERT, Protocol analyzer etc.
Solid understanding of PCB architecture
Comfortable programming in a scripting language (e.g., Python) and writing complete programs from scratch (e.g. 5000+ lines of code)
Comfortable designing/maintaining flows and methodologies from scratch
Ability to break a complex problem into simpler problems and to localize and resolve problems
Well organized, punctual, and excellent communication skills
BS/MS in electrical engineering with 8+ years of experience with at least 5+ years of experience in PCIE and/or Ethernet system validation

Job Responsibility

Design system validation testcases, including PCIE gen 5 and Ethernet106G, based on product application specifications/ customer specifications
Run system validation tests on customer-facing cards, including DPU accelerator cards, on different systems, and ensuring PCB robustness for different testcases
Running Ethernet and PCIE electrical and functional compliance tests, and able to debug issues
Debug complex system-level issues spanning different interfaces and provide robust system solutions for them
Driving system level specifications for the PCBs to meet system requirements
Drive the PCB firmware specifications based on system level specifications
Work on the PCB functional bring up
Automating system validation flows to reduce run time and efficiently post process results
Partner with cross-functional teams, including ASIC, Firmware, and Validation, to ensure seamless product validation

Fulltime

Senior Verification Engineer

System Validation engineers in this group are responsible for driving validation...

Location

India , Bengaluru

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

4-6 Years of Experience
Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering
Experience of Emulation and system level validation for IPs and sub-systems and ASIC products
Emulation build skills and knowledge for a subsystem in at least one emulation system
Execution of the design in emulation platform and knowledge of hardware and software interplay
Knowledge of Validation test content using C, C++
Expertise on hardware behavioral language (Verilog, System Verilog)
Exposure to producing validation specifications and documentation describing sophisticated designs
Ability to work under time-scale pressure and meet ambitious targets without compromising on quality
Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator

Job Responsibility

Work with project team to understand, review the system requirements and deliver emulator testbench specifications
Own the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc.) in emulation environment
Guide other members of the team as needed to enable the successful completion of project activities

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

ASIC Verification - Team Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Santa Clara

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience working with large verification projects, including cluster/subsystem and fullchip environments
Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion
Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements
Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
Comfortable and experienced with AI based tools to accelerate productivity

Job Responsibility

Pre-Silicon Verification
Improves verification efficiency through new and updated methodologies or tools
Defines verification strategies and test plans
Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels
Drives the development of verification environments, runs, and debugs simulations to drive quality
Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals
Performance
Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs
Determines type of performance model needed and appropriate model fidelity

Fulltime

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

New

Engineer III – ASIC Validation & Automation

On behalf of our client, a global technology leader focused on developing innova...

Location

United States , Milpitas

Salary:

50.00 - 55.00 USD / Hour

Tucker Parker Smith Group

Expiration Date

Until further notice

Requirements

B.S. or M.S. in Electrical Engineering, Electronics Engineering, Computer Engineering, or equivalent practical experience
5 years of hands-on experience in ASIC development, validation, or related engineering disciplines
Strong proficiency in automation and scripting, including Python, API integration, and workflow orchestration
Demonstrated expertise with validation frameworks, testing methodologies, and agent development
Strong communication skills with the ability to explain complex technical concepts clearly

Job Responsibility

Translate architectural and design specifications into production-ready agents and implementations
Lead ASIC testing and validation efforts across multiple projects and engineering sites
Execute and manage validation workflows, automation, and framework development
Partner closely with platform, design, and validation teams to offload implementation work and accelerate delivery timelines
Develop and maintain automation solutions using Python, APIs, and workflow orchestration tools
Identify, debug, and resolve complex system-level issues to ensure high reliability and performance
Contribute to best practices, documentation, and continuous improvement initiatives

FPGA Engineer

Hardware Engineers at Optiver build hardware-based trading systems ranging from ...

Location

United States , Austin

Salary:

Not provided

Optiver

Expiration Date

Until further notice

Requirements

A Bachelor’s degree in CE, EE, CS, or related technical field
Experience designing, coding, testing, and verifying FPGAs and/or ASICs
Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++
Experience with RTL synthesis, writing timing, area, and other relevant constraints
Experience with digital simulators and self-checking test benches
Ability to work closely with software developers to rapidly deliver integrated systems

Job Responsibility

Accelerate network infrastructure and trading system components with high speed hardware designs
Research new low-latency techniques and platforms and identify opportunities for integration with our trading system
Work in a multidisciplinary team of traders, software developers, and infrastructure engineers
Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware
Manage relationships with 3rd party vendors

What we offer

The opportunity to work alongside best-in-class professionals from over 40 different countries
A highly competitive compensation package
Global profit-sharing pool and performance-based bonus structure
401(k) match up to 50%
Comprehensive health, mental, dental, vision, disability, and life coverage
25 paid vacation days alongside market holidays
Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

Fulltime

ASIC Engineer Intern, Architecture

Meta is seeking an ASIC Engineer Intern, Architecture to join our Infrastructure...

Location

United States , Sunnyvale

Salary:

6660.00 - 11647.00 USD / Month

FPGA Engineer

Hardware Engineers at Optiver build hardware-based trading systems ranging from ...

Location

United States , New York

Salary:

200000.00 USD / Year

Optiver

Expiration Date

Until further notice

Requirements

Bachelor’s degree in CE, EE, CS, or related technical field
Experience designing, coding, testing, and verifying FPGAs and/or ASICs
Experience coding in VHDL, Verilog, SystemVerilog as well as C or C++
Experience with RTL synthesis, writing timing, area, and other relevant constraints
Experience with digital simulators and self-checking test benches
Ability to work closely with software developers to rapidly deliver integrated systems

Job Responsibility

Accelerate network infrastructure and trading system components with high-speed hardware designs
Research new low-latency techniques and platforms and identify opportunities for integration with our trading system
Work in a multidisciplinary team of traders, software developers, and infrastructure engineers
Leverage the best hardware available or build in-house versions to ensure our FPGAs can interface with cutting edge server hardware
Manage relationships with 3rd party vendors

What we offer

Opportunity to work alongside best-in-class professionals from over 40 different countries
Highly competitive compensation package
Global profit-sharing pool and performance-based bonus structure
401(k) match up to 50%
Comprehensive health, mental, dental, vision, disability, and life coverage
25 paid vacation days alongside market holidays
Extensive office perks, including breakfast, lunch and snacks, regular social events, clubs, sporting leagues and more

ASIC Engineer, Accelerator Systems

Meta

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 14, 2026

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