ASIC Engineer, Accelerator Systems Job at Meta (Bangalore)

Principal Engineer, ASIC Development Engineering (Frontend Architect - AI Storage Solutions)

In this Frontend Architect position, you will develop AI Storage Solutions based...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors or Masters or PhD in Computer/Electrical Engineering with 8+ years of hands-on Architecture experience authoring specifications
Strong technical background architecting SoC and I/O subsystems involving PCIe and PCIe-DMA engines, or UCIe or CXL or UAL
Strong IO subsystem microarchitecture, technical, and working knowledge of the PCIe/UCIe protocol specifications
Knowledge of I/O Subsystem and DMA interactions with internal embedded processor-subsystems (x86, RISC-V or ARM) and external host CPU
Good understanding of computer/graphics architecture, ML, LLM
Architecting an GPU/TPU/xPU Accelerator systems with optimized high bandwidth memory hierarchy and frontend architecture for multi-trillion parameter LLM training/inference including Dense, Mixture of Experts (MoE) with multiple modalities (text, vision, speech)
Deep experience optimizing large-scale ML systems, GPU architectures
Proficiency in principles and methods of microarchitecture, software, and hardware relevant to performance engineering
Multi-disciplinary experience, including familiarity with Firmware and ASIC design
Expertise in CUDA programming, GPU memory hierarchies, and hardware-specific optimizations

Job Responsibility

Responsible for driving the SoC architecture, with a particular focus on I/O subsystems connected over UCIe, PCIe, UAL or CXL
Define I/O subsystem and PCIe DMA architectures, including their interactions with internal embedded processor-subsystems, Network on Chip, Memory controllers, and FPGA fabric
Create flexible and modular I/O subsystem architectures that can be deployed in either chiplet, monolithic or 3D form factors
Work with customers, and cross-functional teams to scope SoC requirements, analyze PPA tradeoffs, and then define architectural requirements that meet the PPA and schedule targets
Define I/O subsystem and DMA hardware, software, and firmware interactions with embedded processing subsystems and SoC CPUs on the device side and Host CPUs
Author architecture specifications in clear and concise language. Guide and assist pre-silicon design/verification and post-silicon validation during the execution phase
Responsible for improving the AI/ML ASIC Architecture performance through hardware & software co-optimization, post-silicon performance analysis, and influencing the strategic product roadmap
LLM Workload analysis and characterization of ASIC and competitive datacenter and AI solutions to identify opportunities for performance improvement in our products
Experience architecting one or some components of AI/ML accelerator ASICs such as HBM, PCIe/UCIe/CXL, NoC, DMA, Firmware Interactions, NAND, xPU, fabrics, etc
Drive the AI Storage Solutions frontend system architecture with GPU/TPU/NPU/xPU to match or exceed the nextgen HBM bandwidth

Fulltime

ASIC Engineer

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Austin

Salary:

158956.00 - 198220.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Bachelor's degree (or foreign equivalent) in Computer Science, Computer Engineering, or a related field
Requires completion of one university-level course, one research project, or one internship involving: Demonstrated knowledge of Computer Architecture and Logic Design fundamentals
RTL development using Verilog, System Verilog or HLS
Exposure to Micro-architecture development
Lint, CDC, Synthesis, & Power Optimization
Synthesis, Timing Closure or Formal Verification Methodology
TCL, Python, Perl, or Shell-scripting

Job Responsibility

Participate in Micro-architecture, Design, and Verification reviews and provide feedback
Design and develop RTL or HLS code for some of the Ips
Analyze designs and enhance PPA (Power, Performance, Area)
Support and develop Verification Infrastructure, analyze and improve Verification Coverage, Support Simulation accelerators and post-Silicon validation
Ensure that the designs are CDC and Lint clean
Get involved in performance discussions and implement power, performance, area aware designs

What we offer

bonus
equity
benefits

Fulltime

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

149000.00 - 162580.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires a Master's degree (or foreign degree equivalent) in Electrical Engineering, Computer Engineering, Computer Science, Electrical and Computer Engineering, Electronics and Telecommunication Engineering or related field
2 years of work experience in the job offered or related occupation
2 years of experience in Verilog, System Verilog/UVM methodology based verification
2 years of experience in Block/IP/sub-system and/or SoC level verification based on System Verilog UVM based methodologies
2 years of experience in EDA tools and scripting (Python, Shell) used to build tools and flows for verification environments
2 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
2 years of experience in Developing and executing verification test plans, random stimulus, coverage, and assertions
2 years of experience in debugging and root cause failures and tracking verification completion using metrics
2 years of experience working in a CPU or GPU or HW Accelerator verification
2 years of experience in executing a full verification cycle

Job Responsibility

Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Define and implement ASIC verification plans, build verifications test benches to block IP/subsystem/ SoC level verification and develop functional tests
Debug, rootcause and resolve functional failures in the design, partnering with the Design team
Collaborate with crossfunctional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

Fulltime

Software Engineer, Systems ML - Compilers / Backend

We are seeking a software engineer to support the development of the compiler to...

Location

United States , Sunnyvale

Salary:

181000.00 USD / Year ▼

Meta

Expiration Date

Until further notice

Requirements

Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
Experience in software design and programming experience in Python and/or C/C++ for development, debugging, testing and performance analysis
Experience in AI framework development or accelerating models on hardware architectures (GPU, TPU, custom AI ASICs)
Must obtain work authorization in the country of employment at the time of hire, and maintain ongoing work authorization during employment

Job Responsibility

Analyze and design effective compiler passes and optimizations. Implement and/or enhance code generation targeting machine learning accelerators
Work with algorithm research teams to support the co-design of hardware features mapping ML graphs to hardware implementations, modeling data-flows, creating cost-benefit analysis and estimating silicon power and performance
Work with hardware architects to co-design hardware features that maximize performance, power efficiency and programmability
Contribute to the development of machine-learning libraries, intermediate representations, export formats, and analysis tools
Collaborate with the team to enhance the efficiency, scalability, and stability of our toolchains by focusing on kernel optimization and tuning
Conduct design and code reviews. Evaluate code performance, debug, diagnose and drive resolution of compiler and cross-disciplinary system issues
Interface with other compiler-focused teams to evaluate and incorporate their innovations and vice versa

What we offer

bonus
equity
benefits

ASIC Engineer, Design Verification

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

186000.00 - 192170.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires a Bachelor's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field, followed by 3 years of work experience in the job offered or a computer-related occupation
Requires 3 years of experience in Verilog, System Verilog/UVM methodology based verification
Requires 3 years of experience in Block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM based methodologies
Requires 3 years of experience in EDA tools and scripting (C++ or Python, Shell) used to build tools and flows for verification environments
Requires 3 years of experience in Implementing Design Verification infrastructure (Testbench, Functional coverage, Regression setup)
Requires 3 years of experience in Developing and executing verification testplans, random stimulus, coverage
Requires 3 years of experience in Debugging and root cause failures and tracking verification completion using metrics
Requires 3 years of experience in Working in a CPU or GPU or SOC or HW Accelerator verification
Requires 3 years of experience in Executing a full verification cycle

Job Responsibility

Develop functional tests based on verification test plan
Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
Define and implement ASIC verification plans, build verifications test benches to block IP/sub-system/SoC level verification and develop functional tests
Debug, root-cause and resolve functional failures in the design, partnering with the Design team
Collaborate with cross-functional teams like Design, Architecture/Modeling, Emulation and Silicon validation teams towards ensuring the highest design quality

What we offer

bonus
equity
benefits

ASIC Engineer, Architecture

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Seattle

Salary:

198450.00 - 234520.00 USD / Year

Meta

Expiration Date

Until further notice

Requirements

Requires Master’s degree (or foreign degree equivalent) in Electrical Engineering, or a related field followed by 24 months of experience in the job offered or in a related occupation
Requires 24 months of experience in the following: Coding in C, C++, Python
Conducting design reviews
Object-oriented software development
Analyze algorithms and enhanced architecture
Software development tools: Code editors (VIM or Emacs), and revision control systems (Git) and Linux, UNIX including file manipulation and simple commands

Job Responsibility

Build accelerators for Meta's top workloads enabling the data centres to scale efficiently
Work on developing Data Centre ASIC architecture, algorithms, models, Bootloaders or tools
Help architect state-of-the art machine learning accelerators and contribute to modelling these accelerators
Support performance modelling of the accelerators using C++
Verify stability, interoperability, portability, security, and scalability of system architecture

What we offer

bonus
equity
benefits

Staff Engineer, ASIC development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
5-8+ years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases
Hands-on experience in post-silicon ASIC bring-up, validation, and debug
Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis

Fulltime

ASIC Engineer Intern, Design

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organi...

Location

India , Bangalore

Salary:

Not provided

Meta

Expiration Date

Until further notice

Requirements

Currently has, or is in the process of obtaining, a Bachelor's degree in Electrical Engineering, Computer Engineering or related engineering fields
Knowledge of Verilog or System Verilog or HLS
Knowledge of Computer Architecture and Logic Design fundamentals
Must obtain work authorization in the country of employment at the time of hire and maintain ongoing work authorization during employment
Intent to return to degree-program after the completion of the internship/co-op

Job Responsibility

Participate in Micro-architecture, Design, and Verification reviews and provide feedback
Design and develop RTL or HLS code for some of the IPs
Analyze designs and enhance PPA (Power, Performance, Area)
Support and develop Verification Infrastructure, analyze and improve Verification Coverage
Support Simulation accelerators and post-Silicon validation

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ASIC Engineer, Accelerator Systems

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