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ASIC Emulation Engineer - Infra Silicon Enablement

India, Bangalore · Job Posted March 04, 2026
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Job Description

Meta is hiring ASIC Engineers within the Infrastructure organization. We are looking for individuals with experience in the Pre/Post Silicon Validation to build and scale silicon for data center applications. As an ASIC Engineer in the Infra Silicon Enablement team, you will be part of a dynamic team working with the best in the industry, focused on developing and supporting innovative ASIC solutions for Meta’s data center applications.

Job Responsibility

  • Work across all aspects of silicon lifecycle to deliver reliable and performant silicon solutions. From early architecture and design inputs, pre-silicon test readiness/validation, post-silicon bring-up, validation, characterization and deployment in fleet
  • Create/develop validation plan, tests and automation tool sets targeted at silicon validation and productization. Inclusive of, but not limited to silicon diagnostics, performance analysis, debug tools, bare metal and full stack systems, from early labs to data center deployments
  • Understand production system use cases to improve silicon validation
  • Provide feedback into next generation architecture and design with insights from the production fleet
  • Root-cause, resolve and remediate issues with silicon across the product lifecycle
  • Lead end-to-end silicon validation effort, driving strategy, planning, execution, and post-silicon enablement to ensure successful product delivery

Requirements

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience with ASIC development cycles, Pre/Post Silicon Validation
  • 6+ years of experience with troubleshooting, debug and analytics for Silicon products
  • Experience in Python, C/C++ and/or similar languages (data structures, algorithms, and OOP)
  • Experience working with internal and external partners for ASIC and/or systems development
  • Experience in ASIC Design or Development, Emulation and Post Silicon validation

Nice to have

  • 6+ years of experience with Hardware Emulation, Verification, Prototyping & emulation model builds and flows on Palladium, Protium & Zebu Platforms
  • Exposure to networking SoCs and AI SoCs, including bring-up, validation, and performance optimization in emulation environments
  • Experience in driving improvements for emulation efficiency, automation, and capacity planning
  • Experience in Verilog, System Verilog, C/C++
  • Familiarity with industry best practices for model build, release, and qualification
  • Knowledge of Processor Designs, GPUs , Debug Subsystem is highly desirable
  • Exposure of PCIe, USB, Ethernet, and networking domain protocols
  • Experience with AI training and inference accelerators, including bring-up and validation

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