ASIC Digital Design Principal Engineer Job at Synopsis Engineering (Bengaluru)

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
8+ years of experience in ASIC development, with a proven track record of leading complex project
Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
Strong digital design development and execution skills , solving bugs
Experience in grooming team of 1-4 engineers, interacting with many team
Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
Hands-on experience with industry-standard EDA tools and design flows
Deep knowledge on PCIe, axi , DMA, AHB interfaces
Expertise in high-performance and low-power design techniques
Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly

Job Responsibility

Design and implements IPs and subsystems
Dealing the best of class IPs for all SanDisk products

Fulltime

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug
5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic

Job Responsibility

Part of the design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and strong teamwork

Fulltime

Principal Engineer, VLSI Design Engineering

Principal Engineer role in VLSI Design Engineering focusing on SOC Verification....

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

8+ Years of relevant Logic Verification experience
Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
Create verification environment using UVM methodology
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage driven verification closure
Work with architects, designers, and post-silicon teams
Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
Development of tools for Design and Verification support
Debug failures and root-cause it by interacting with other teams/groups
Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis

Job Responsibility

Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
Create verification environment using UVM methodology
Create reusable bus functional models, monitors, checkers and scoreboards
Drive functional coverage driven verification closure
Work with architects, designers, and post-silicon teams
Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
Development of tools for Design and Verification support
Debug failures and root-cause it by interacting with other teams/groups

Fulltime

New

Kitchen Porter

We are looking for a reliable, hard-working, and enthusiastic Kitchen Porter to ...

Location

United Kingdom , Portrush

Salary:

8.00 - 12.71 GBP / Hour

360 Resourcing Solutions

Expiration Date

Until further notice

Requirements

Reliability: Proven record of punctuality and reliability
Physical Stamina: Ability to stand for long periods, work in a warm environment, and lift heavy items (e.g., crates of deliveries)
Team Player: Positive attitude and the ability to work well as part of a close-knit team
Speed & Efficiency: Capable of working quickly under pressure during busy lunchtime or weekend rushes
Experience: Previous experience as a Kitchen Porter or in a cafe/hospitality setting is a plus but not essential—we will provide training
Right to work in the UK

Job Responsibility

Dishwashing: Operating the industrial dishwasher, washing pots, pans, plates, and cutlery, and ensuring they are dried and restocked quickly
Kitchen Hygiene: Cleaning and sanitising work surfaces, walls, floors, and food preparation areas (sinks, stoves, fridges) before, during, and after shifts
Support: Assisting with basic food prep, such as washing, peeling, and chopping vegetables or fruit when needed
Waste Management: Emptying kitchen bins and ensuring all waste is sorted into recycling/disposal areas
Stock Management: Receiving deliveries, checking them for accuracy, and organizing the stockroom and walk-in fridges
Safety Adherence: Following all health, safety, and hygiene regulations, including COSHH (Control of Substances Hazardous to Health) standards
General Cleaning: Assisting with maintaining the cleanliness of the cafe seating area, staff rooms, or public restrooms if requested

What we offer

A supportive and welcoming team environment
50% staff card to use on shift and with friends & family!
Unlimited free hot drinks on shift!
Free cake on your birthday!
Company pension!
Length of service recognition!
Opportunities to grow your career!

New

Head of Corporate Expenses

The Head of Corporate Expenses role is a senior management level position report...

Location

United States , New York

Salary:

250000.00 - 500000.00 USD / Year

Citi

Expiration Date

May 21, 2026

Requirements

15+ years of relevant experience
10+ years of managerial experience
Experience leading functional teams and driving Financial Planning and Analysis
Demonstrated experience with quantitative analysis, financial analysis across retail and investment banking products, performance analysis, project management of financial planning projects, developing data reporting, and analytics processes for financial services industry
Proficient Microsoft Office skills with an emphasis on Excel and PowerPoint
Ability to influence and advise senior stakeholders
Demonstrated leadership and project management skills
Consistently demonstrates clear and concise written and verbal communication
Bachelor's degree/University degree or equivalent experience
Master's degree preferred

Job Responsibility

Drive forward looking processes including annual budget plan, monthly outlooks, and multi-year strategic plans as well as drive transformation and strategy agenda
Oversee staff within the relevant infrastructure area as well as direct and control strategy and execution of firm activities within a major infrastructure area
Oversee functional team responsible for performance reporting and forward-looking processes such as analysis of quarter end flash estimates, creating variance analysis, and commentary for senior management
Design new or re-engineer existing financial or business processes to drive centralization and standardization of Financial Planning and Analysis (FP&A) activities based on global common standards
Define and refine the expense calculation methodology to ensure accuracy and consistency across the organization
Generate detailed expense commentary at a function-specific level for all financial scenarios, including actuals
Drive content and standards for management review processes including quarterly CEO and CFO business reviews
Utilize knowledge of quantitative analysis to develop firm-wide data and analytics requirements and ensure business and FP&A have information to support performance management processes aligned to strategic plans
Prepare and present financial presentations for senior management and other stakeholders that drive business decisions as well as partner with front office businesses or functional areas to improve efficiency, effectiveness, productivity, and/or controls
Manage a functional team to perform analysis of the financial performance of Citi and its competitors

What we offer

medical, dental & vision coverage
401(k)
life, accident, and disability insurance
wellness programs
paid time off packages, including planned time off (vacation), unplanned time off (sick leave), and paid holidays

Fulltime

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ASIC Digital Design Principal Engineer

Synopsis Engineering

Location:
India , Bengaluru

Category:
IT - Software Development

Contract Type:
Employment contract

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 24, 2026

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