Asic digital design engineer Job at Idaho Scientific (Boise)

Senior/Principal ASIC Digital Design Engineer

Idaho Scientific designs and deploys secure system solutions through novel CPU d...

Location

United States , Boise; Salt Lake City

Salary:

Not provided

Idaho Scientific

Expiration Date

Until further notice

Requirements

US Citizenship (no exceptions)
Proven work experience designing and fabricating an ASIC (no exceptions)
Ability to get a security clearance
Solid technical background with at least 5 years of experience in FPGA or ASIC product development
Ability to communicate clearly in person and in written documentation
Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
Strong analytical and problem solving skills
Extreme attention to detail
A willingness to roll up one’s sleeves to get the job done

Job Responsibility

Collaborate with team leaders to explore and clearly identify real problems and solutions
Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages
Integrate complex systems that instantiate both Idaho Scientific and third party IP
Contribute to all aspects of design success from specification to production
Apply our state-of-the-art IP to ASIC and FPGA products in the real world
Define and improve high-quality design methods and processes
Mentor and guide other ASIC design engineers

What we offer

Competitive Pay
Flexible Work Schedule
Health Benefits and Insurance
Retirement fund contributions
Profit Sharing
Generous Paid Time Off Policy

Fulltime

ASIC Digital Design Principal Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

India , Bengaluru

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering (BSEE/MSEE) or related field
Minimum 6 years of experience in bare metal firmware development and silicon testing
Strong understanding of digital design (RTL) and mixed-signal integration principles
Experience with structured firmware development, verification, and documentation processes
Proficiency in project execution, from initial specification through to final testing and validation
Knowledge of SerDes standards and scripting (Shell/Python) is a strong advantage

Job Responsibility

Designing, developing, and testing bare metal firmware for advanced mixed-signal ASICs, with a focus on high-speed SerDes products
Collaborating with analog and digital teams to define specifications and integration requirements for IP blocks and system-on-chip (SoC) solutions
Executing structured firmware development processes, including verification and thorough documentation of design flows
Performing functional and performance tests on prototype test-chips to ensure robust operation and compliance with design specifications
Supporting customer teams by providing technical expertise, troubleshooting, and guidance throughout the product lifecycle
Contributing to project planning, tracking milestones, and ensuring timely delivery of high-quality deliverables
Engaging in continuous learning to stay abreast of industry advancements in SerDes standards, scripting, and digital design methodologies

What we offer

Comprehensive medical and healthcare plans that work for you and your family
Time Away in addition to company holidays, we have ETO and FTO Programs
Family Support maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
ESPP Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement Plans save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

ASIC Digital Design, Sr Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Canada , Nepean

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

Master’s degree in Electrical Engineering or related field
At least 5 years of relevant industry experience
Proficient in Verilog or VHDL for digital design and verification
Strong familiarity with code quality metrics and methodologies
Experience in high-speed digital and mixed-signal design, including asynchronous clock crossings and DFT methodologies
Deep understanding of CDC, synthesis, and power optimization techniques
Simulation experience and the ability to debug collaboratively with verification teams
Excellent organizational and communication skills, with the ability to interface with various design groups and customer support teams

Job Responsibility

Designing and verifying complex ASIC digital and mixed-signal systems using Verilog or VHDL
Analyzing digital and analog specifications to develop robust system-level designs
Collaborating on design flow analysis for CDC, synthesis, DFT, and low power methodologies to optimize performance and reliability
Developing, executing, and tracking comprehensive test plans to ensure thorough verification coverage
Performing and analyzing functional, assertion, and code coverage to validate design integrity
Investigating failure cases, debugging issues, and running gate-level simulations to drive resolution and product quality
Working closely with cross-disciplinary teams to ensure seamless integration and alignment across the design lifecycle

What we offer

Comprehensive medical and healthcare plans
ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Retirement plans
Competitive salaries

Fulltime

ASIC Digital Design, Sr Staff Engineer

Our Hardware Engineers at Synopsys are responsible for designing and developing ...

Location

Portugal , Moreira, Porto

Salary:

Not provided

Synopsis Engineering

Expiration Date

Until further notice

Requirements

6-10 years of hands-on experience in FPGA design and verification, with a focus on IP-level functional verification
Proficiency in Verilog and MATLAB for digital design, verification, and FPGA prototyping with logical synthesis flows
Strong programming and scripting skills for test automation and data analytics (Python, C/C++, TCL)
Strong understanding of digital and mixed-signal circuit evaluation, troubleshooting, and performance optimization techniques
Ability to interpret and apply digital architecture and SerDes standards documentation to develop robust verification solutions
Excellent technical documentation skills to ensure clear communication and knowledge transfer

Job Responsibility

Interpreting SerDes standards and digital, analog, and firmware architecture documents to develop verification environments and regression testcases in MATLAB
Evaluating and troubleshooting digital and mixed-signal circuits to ensure optimal performance and resolve complex design challenges
Collaborating with digital, firmware, and analog teams to solve verification challenges and improve design methodologies
Adapting and debugging internal verification environments to effectively replicate challenging scenarios
Identifying and implementing process improvements to enhance efficiency in design procedures and methodologies
Documenting verification environments, plans, and procedures to ensure clear communication and knowledge sharing across teams

What we offer

Comprehensive medical and healthcare plans that work for you and your family
In addition to company holidays, we have ETO and FTO Programs
Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
Save for your future with our retirement plans that vary by region and country
Competitive salaries

Fulltime

Staff Digital Design Engineer - DSP

This is an outstanding opportunity for an experienced engineer passionate about ...

Location

United Kingdom , Edinburgh

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proven experience in DSP algorithm development and implementation for SerDes, wireless communications or high-speed serial interfaces (Ethernet, PCIe, etc.)
Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation
Strong background and experience in digital design techniques including clock domain crossing, RTL (preferably SystemVerilog), and ASIC front-end design tools and flows
Understanding of power analysis and techniques for optimization of digital designs for low power
Familiarity with simulation and modeling of DSP blocks in SerDes

Job Responsibility

Collaborate with architects, hardware, and verification engineers to refine and implement new DSP features for cutting-edge and next-generation SerDes transceivers with a focus on low power
Implement DSP algorithms for equalization, filtering and sequence detection
RTL development and using front-end ASIC tools (lint, synthesis, STA) to ensure the highest quality code
Develop comprehensive documentation detailing DSP algorithm interactions with SerDes hardware and software components

Fulltime

Senior FPGA ASIC Design Engineer

Join a team at the forefront of computing innovation. This is an exceptional opp...

Location

United Kingdom , Penicuik

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Strong experience with modern, complex digital processing architectures
Deep understanding of FPGA and ASIC design flows, tools, and system-level design
Solid software development and integration skills
A proven track record of technical leadership, mentoring engineers, and driving projects from concept to delivery

Job Responsibility

Lead technical discussions and collaborate with system architects, hardware, and software engineers to define and deliver new features
Act as a technical mentor to junior engineers through design reviews, best-practice guidance, and day-to-day support
Design and implement high-quality, high-performance RTL for new features, modules, and systems
Develop software and scripts to configure, control, and test hardware modules and systems
Create clear, detailed documentation describing designs and interactions with hardware and software components
Debug complex system-level issues, identify root causes, and partner with verification teams to deliver robust solutions
Estimate development schedules and test-environment needs, and support junior engineers with project planning
Champion continuous improvement in design, validation, and development workflows
Take on increasing leadership responsibilities, with a clear path toward senior technical or team management roles

Fulltime

Digital Design Engineer

Meta is seeking highly skilled Design Engineers to join our team. In this role, ...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

ASIC Engineer, Design

Meta is seeking highly skilled Design Engineers to join our team. In this role, ...

Location

United States , Sunnyvale

Salary:

146000.00 - 209000.00 USD / Year

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Asic digital design engineer

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