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ASIC Design Verification Engineer

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Duo Security

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Location:
India , Bangalore

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We craft the networking hardware for Enterprises and Service Providers, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by crafting, developing and testing some of the most sophisticated ASICs being developed in the industry. You will engage in dynamic collaboration with verification engineers, designers, and multi-functional teams, working together to ensure the successful verification of the ASIC throughout its lifecycle.

Job Responsibility:

  • Architect block, cluster and top-level DV environment infrastructure
  • Develop DV infrastructure from scratch
  • Maintain and improve existing DV environments
  • Develop test plans and tests for qualifying design at block, cluster and higher-level environments with mix of constraint random and advised stimulus
  • Ensure complete verification coverage through implementation and review of code and functional coverage
  • Ensure RTL quality with qualifying the design with Gate Level Simulations on netlist
  • Collaborate closely with designers, architects, and software teams to address and debug issues during post-silicon bring-up, ensuring seamless integration and efficient performance
  • Support testing of design in emulation
  • Lead all aspects of and manage the ASIC bring-up process

Requirements:

  • Bachelor's Degree or equivalent experience in EE, CE, or other related field
  • 7+ years of related ASIC design verification experience
  • Proficient in ASIC verification using UVM/System Verilog
  • Proficient in verifying sophisticated blocks, clusters and top level for ASIC
  • Experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes

Nice to have:

  • Scripting experience with Perl and/or Python
  • Experience with data path verification, performance tests
  • Experience with Veloce/Palladium/Zebu/HAPS
  • Formal verification (iev/vc formal) knowledge
  • Demonstrated ability on one or more protocols (PCIe, Ethernet, RDMA, TCP)

Additional Information:

Job Posted:
May 05, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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