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The focus of this role is to plan, build, and execute the verification of new and existing features for AMD’s wired networking IP, resulting in no bugs in the final design.
Job Responsibility:
Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
Requirements:
Proficient in IP level ASIC verification
Proficient in debugging RTL code using simulation tools
Expert in the UVM concepts and SystemVerilog language
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced in developing UVM based verification frameworks and testbenches, processes and flows
Comfortable automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, formal verification
Scripting language experience: Perl, Python, Makefile, shell preferred
Exposure to leadership or mentorship is an asset
Prior exposure to networking protocols such as Ethernet, UAL, LLR, CBFC is desired
Experienced in using AI tools
Nice to have:
Leadership or mentorship experience
Exposure to networking protocols such as Ethernet, UAL, LLR, CBFC
Experience using AI tools
What we offer:
Benefits offered are described at AMD benefits at a glance