ASIC Design Intern Job at Hewlett Packard Enterprise (Heredia)

Analog and Mixed Signal ASIC Design Intern

Teradyne’s Semiconductor Test Division at our Agoura Hills, CA facility is looki...

Location

United States , Agoura Hills

Salary:

25.50 - 47.00 USD / Hour

Teradyne

Expiration Date

Until further notice

Requirements

Currently working towards their BSEE/MSEE degree with emphasis on mixed-signal and analog integrated circuit design
Analog and/or Mixed-Signal integrated circuit design knowledge
Cadence EDA tools, Spectre, Hspice
Programming and Scripting, C++, VBA, Python
Knowledge working with lab equipment - oscilloscopes, DMM, etc.
Excellent written and verbal communication skills
Detail-oriented and possess excellent follow-up skills
Ability to work independently with minimal direction
Must be available for a min of 3 months Summer 2026

Job Responsibility

Assist design engineers in developing specifications for analog blocks
Assist design engineers to optimize and characterize a circuit via simulation (with Cadence EDA tools) over all process and operating conditions
Take part in the Physical implementation (layout) of circuits
Participate in documentation
Be part of the design review
Participate in IC evaluation in the lab

Fulltime

ASIC Engineer Intern, Design

Meta is seeking an ASIC Design Engineer Intern to join our Infrastructure organi...

Location

India , Bangalore

Salary:

Not provided

Asic engineer intern, design verification

Meta is seeking an ASIC Engineer Intern to join our Infrastructure organization....

Location

India , Bangalore

Salary:

Not provided

ASIC Design Engineer

This role has been designed as ‘Onsite’ with an expectation that you will primar...

Location

United States , Sunnyvale

Salary:

120000.00 - 243000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 4+ years of relevant experience
Strong analytical/problem solving skills
Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus
Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired
Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired
Excellent written and verbal communications skills are good to have
Knowledge of Perl/Python is a plus
Experience with AI agentic tools is a plus

Job Responsibility

Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target
Work with the Verification team to make sure your block is fully validated
Provide mentoring/guidance to new college-grad engineers and interns

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Intern

ASIC Post-Si Verification Engineering Intern to join our team in Roseville, CA. ...

Location

United States , Roseville

Salary:

35.00 - 40.25 USD / Hour

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Currently pursuing a Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering or a related technical field
At least 3rd Year of engineering courses completed
Basic programming or scripting knowledge (e.g., Verilog, SystemVerilog Python, PERL, TCL, C, C++)
Experience with hardware design
Strong interest in high-tech and a passion for learning
Excellent communication and interpersonal skills
Strong problem-solving and analytical skills
Ability to work within a team environment

Job Responsibility

Working with the HPE Aruba ASIC development team on next generation products
Having a summer project that will be used for/in the development activities of current or future ASIC's
Working with and learning from the senior members of the ASIC / VLSI team
Responsibilities may include RTL/Physical Design, Pre-Silicon verification
Post-Silicon verification
Formal Verification
Script &/or Tool development
schedule breakdowns, document generation, and several other possible duties

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Asic Design Engineer Iv

The successful candidate is considered an emerging authority, who applies extens...

Location

United States , Home

Salary:

101326.82 - 243486.84 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor degree in Hardware or Electrical Engineering (EE) with 8-10 years of experience, Masters degree in Hardware or Electrical Engineering (EE) with 6-8 years of experience or a PhD in Hardware or Electrical Engineering (EE) with 3-5 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Perform packaging and an evaluation board for the physical chip
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

ASIC Design Engineer III

Location

United States , Home, New York

Salary:

82437.89 - 198097.02 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Packaging and an evaluation board for the physical chip must also be performed
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs

Fulltime

ASIC Design Team Lead

Location

United States , Home

Salary:

130611.87 - 239061.79 USD / Year

Arcfield

Expiration Date

Until further notice

Requirements

Bachelor degree in Hardware or Electrical Engineering (EE) with 12-15 years of experience or a Master's degree in Hardware or Electrical Engineering (EE) with 10-13 years of experience or a Ph.D in Hardware or Electrical Engineering (EE) with 10+ years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim

Job Responsibility

Lead a team of ASIC design engineers to create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) and reset domain crossing (RDC) verification
Perform Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Help the design team run static timing analysis and power analysis after the CTS and place and route
Packaging and an evaluation board for the physical chip must also be performed
Supervise the development and maintenance of technical procedures, documentation, and manuals and lead the Design team to compile and analyze operational data and direct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

What we offer

Health Insurance
Life Insurance
Paid Time Off
Holiday Pay
Short Term and Long-Term Disability
Retirement and Savings
Learning and Development opportunities
wellness programs as well as other optional benefit elections

Fulltime

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ASIC Design Intern

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