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ASIC Design Engineer

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Hewlett Packard Enterprise

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Location:
United States , Sunnyvale

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Category:
IT - Software Development

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Contract Type:
Employment contract

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Salary:

120000.00 - 243000.00 USD / Year
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Job Description:

This role has been designed as ‘Onsite’ with an expectation that you will primarily work from an HPE office. HPE Networking is a leading provider of advanced routers and switches for the internet. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches. Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips. As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow. Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture.

Job Responsibility:

  • Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements
  • Implement the design using Verilog or System Verilog
  • Write functional coverage/SVA to help verification catch corner case bugs
  • Work with the Physical Design team for optimal floorplan and timing closure
  • Identify and fix timing in RTL to meet the frequency target
  • Work with the Verification team to make sure your block is fully validated
  • Provide mentoring/guidance to new college-grad engineers and interns

Requirements:

  • Bachelor’s degree in Electrical Engineering required (Master’s strongly desired) with 4+ years of relevant experience
  • Strong analytical/problem solving skills
  • Knowledge of Computer Architecture/networking protocols through graduate level courses or prior work is a plus
  • Strong coding skills in Verilog/System Verilog through courses/projects and previous work experience is desired
  • Knowledge of synthesis/lint and other state-of-the-art EDA tools is desired
  • Excellent written and verbal communications skills are good to have
  • Knowledge of Perl/Python is a plus
  • Experience with AI agentic tools is a plus

Nice to have:

  • Knowledge of Computer Architecture/networking protocols
  • Knowledge of Perl/Python
  • Experience with AI agentic tools
  • Excellent written and verbal communications skills
What we offer:
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion

Additional Information:

Job Posted:
May 09, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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