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The successful candidate is considered an emerging authority, who applies extensive technical expertise, develops technical solutions to complex problems and exercises considerable latitude in determining objectives and approaches to assignment.
Job Responsibility:
Create a design document that defines the chip's features, performance, and internal components
Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
Verify the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
Develop and port the RTL to an FPGA prototyping board
Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
Run static timing analysis and power analysis after the CTS and place and route
Perform packaging and an evaluation board for the physical chip
Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes
Requirements:
Bachelor degree in Hardware or Electrical Engineering (EE) with 8-10 years of experience, Masters degree in Hardware or Electrical Engineering (EE) with 6-8 years of experience or a PhD in Hardware or Electrical Engineering (EE) with 3-5 years of experience
Must be able to obtain and maintain a Secret clearance
Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
Minimum 3 years experience using Cadence Virtuoso
Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
Minimum 3 years experience using ModelSim/QuestaSim