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Arcfield Logo Arcfield · IT - Software Development

ASIC Design Engineer III

United States, Home, New York 82437.89 - 198097.02 USD / Year · Job Posted April 23, 2026
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Job Responsibility

  • Create a design document that defines the chip's features, performance, and internal components
  • Finish developing, enhancing, and debugging the VHDL/Verifog for the chip
  • Verifying the functionality of the design on an HDL simulator (such as ModelSim or Xcelium) and synthesis with Synopsys or Genus
  • Perform clock domain crossing (CDC) & reset domain crossing (RDC) verification, Design for Test (DFT) and add specific related logic (i.e. memory BIST and JTAG scan chains) to the design
  • Develop and port the RTL to an FPGA prototyping board
  • Perform place and route of the netlist prior to tapeout, this includes clock tree synthesis (CTS)
  • Run static timing analysis and power analysis after the CTS and place and route
  • Packaging and an evaluation board for the physical chip must also be performed
  • Develop and maintain technical procedures, documentation, and manuals and compile and analyze operational data and conduct tests to establish standards for new designs or modifications to existing equipment, systems, or processes

Requirements

  • Bachelor's (or equivalent) with 5-7 years of experience, or a Master's with 3-5 years of experience or a PhD with 0-2 years of experience
  • Must be able to obtain and maintain a Secret clearance
  • Minimum 3 years experience with targeting VHDL designs to Xilinx FPGA's
  • Minimum 3 years experience using Cadence Virtuoso
  • Minimum 5 years experience developing in VHDL and Verilog (or system Verilog)
  • Minimum 3 years experience using ModelSim/QuestaSim

What we offer

  • Health Insurance
  • Life Insurance
  • Paid Time Off
  • Holiday Pay
  • Short Term and Long-Term Disability
  • Retirement and Savings
  • Learning and Development opportunities
  • wellness programs
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