CrawlJobs Logo

ASIC Design Architect

https://www.hpe.com/ Logo

Hewlett Packard Enterprise

Location Icon

Location:
United States

Category Icon

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

148000.00 - 340500.00 USD / Year

Job Description:

We are seeking a highly experienced ASIC Networking Architect to join our architecture team and help us drive the next-generation networking ASICs. This role requires deep technical expertise in computer architecture, high-speed networking protocols, and silicon design methodologies. The ideal candidate will work cross-functionally with system architects, software, and hardware teams to develop innovative, high-performance ASIC solutions for switching, and datacenter connectivity.

Job Responsibility:

  • Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
  • Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
  • Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
  • ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
  • Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
  • Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
  • Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
  • Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
  • Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

Requirements:

  • Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
  • Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
  • Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
  • Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
  • ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
  • High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
  • Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
  • Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
  • Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Nice to have:

  • Experience with programmable pipelines and network switch SoCs
  • Prior involvement in datacenter-scale networking
  • Hands-on knowledge of AI/ML accelerators for networking workloads
  • Contributions to IETF/IEEE standards committees
What we offer:
  • Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
  • Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
  • Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Additional Information:

Job Posted:
April 23, 2025

Employment Type:
Fulltime
Work Type:
On-site work
Job Link Share:

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for ASIC Design Architect

Asic Engineer

This role involves designing, analyzing, and developing ASIC hardware systems as...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 7+ years of ASIC design experience
  • Strong Verilog RTL coding skills
  • Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
  • Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
  • Knowledge of high performance memory subsystems
  • Knowledge of multi-domain clock synchronization and high-speed serial interfaces
  • Strong problem solving and ASIC debugging skills
  • Excellent written and verbal communications skills
  • MSEE or BSEE is required
Job Responsibility
Job Responsibility
  • Define and architect high-performance blocks for the latest, most advanced networking ASICs
  • Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
  • Collaborate with the verification team in the development of the testplan and assist in debugging test failures
  • Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What we offer
What we offer
  • Comprehensive suite of benefits for physical, financial, and emotional wellbeing
  • Specific programs for career development
  • Open communications, empowerment, innovation, teamwork, and customer success culture
  • Pay for performance culture
  • Fulltime
Read More
Arrow Right

Rtl design lead - cpu team

At AMD, our mission is to build great products that accelerate next-generation c...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 6+ years of experience in Digital IP/ASIC design and Verilog RTL development
  • Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification
  • Well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation
  • Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects
  • Should possess expertise in front-end EDA tools sign-off and its flows
  • Familiarity with low power design and low power flow is an added plus
  • Ability to program with scripting languages such as Python or Perl is a plus
  • Highly motivated to seek out solutions and willing to learn new skills to fulfill job requirements
  • Proven interpersonal skills, leadership and teamwork
  • Excellent writing skills in the English language, editing and organizational skills required
Job Responsibility
Job Responsibility
  • RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design
  • Architect and design of power management features, cache, coherency
  • Design optimization for implementing power efficient IP, implementing the RTL using low power techniques
  • Responsible for the inter IP integration issues resolution
  • Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem
  • Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design
  • Architecting, micro-architecting and documentation of the design features
  • Lead design team from all aspects of the RTL deliverables
  • Mentor the junior members of the RTL team to meet the team goals
  • Represents AMD to the outside technical community, partners and vendors
Read More
Arrow Right

ASIC Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 3+ years of ASIC design experience
  • Strong Verilog RTL coding skills
  • Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
  • Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
  • Knowledge of high performance memory subsystems
  • Knowledge of multi-domain clock synchronization and high-speed serial interfaces
  • Strong problem solving and ASIC debugging skills
  • Excellent written and verbal communications skills
  • MSEE or BSEE is required
Job Responsibility
Job Responsibility
  • Define and architect high-performance blocks for the latest, most advanced networking ASICs
  • Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
  • Collaborate with the verification team in the development of the test plan and assist in debugging test failures
  • Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
  • Fulltime
Read More
Arrow Right

ASIC Design Verification Engineer

As a Design Verification engineer on the ASIC team, you will ensure that the ASI...
Location
Location
United States , Santa Clara
Salary
Salary:
106400.00 - 172150.00 USD / Year
paloaltonetworks.com Logo
Palo Alto Networks
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS in EE, CE, or CS required or equivalent military experience required
  • MSEE preferred
  • Minimum 3 years experience in ASIC design verification
  • Demonstrated success in taking multiple ASIC products from concept to mass production
  • Expertise in SystemVerilog and UVM
  • Technical strength in the following areas is required: Defining test plans, including comprehensive adversarial testing
  • Developing rich functional coverage models
  • Creating powerful and scalable test benches
  • Implementing sophisticated self-checking infrastructure with reference models and scoreboards
  • Developing reusable constrained-random tests
Job Responsibility
Job Responsibility
  • Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
  • Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
  • Develop flows, methodologies, and infrastructure for emulation
  • Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
  • Define new tools and methodologies to continuously improve quality and velocity
  • Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification
  • Fulltime
Read More
Arrow Right

Principal ASIC Design Verification Engineer

As a Design Verification engineer on the ASIC team, you will ensure that the ASI...
Location
Location
United States , Santa Clara
Salary
Salary:
173600.00 - 280700.00 USD / Year
paloaltonetworks.com Logo
Palo Alto Networks
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • BS in EE, CE, or CS required or equivalent military experience required
  • MSEE preferred
  • Minimum 5 years experience in ASIC design verification
  • Demonstrated success in taking multiple ASIC products from concept to mass production
  • Expertise in SystemVerilog and UVM
  • Technical strength in the following areas is required: Defining test plans, including comprehensive adversarial testing
  • Developing rich functional coverage models
  • Creating powerful and scalable test benches
  • Implementing sophisticated self-checking infrastructure with reference models and scoreboards
  • Developing reusable constrained-random tests
Job Responsibility
Job Responsibility
  • Collaborate with engineers in software, architecture, design, and verification teams to create comprehensive pre-silicon verification plans across simulation, emulation, and formal verification
  • Plan and execute every aspect of simulation test plans using sophisticated coverage-driven, constrained-random methodologies
  • Develop flows, methodologies, and infrastructure for emulation
  • Create, run, and debug emulation tests in close collaboration with system architects, software engineers, and ASIC designers
  • Define new tools and methodologies to continuously improve quality and velocity
  • Create powerful programs in Python to automate triage, coverage closure, and metrics-driven verification
  • Fulltime
Read More
Arrow Right

Engineer - ASIC

We are hiring for our new Silicon R&D center in Bangalore. Join our team as we p...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
ericsson.com Logo
Ericsson
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in electrical or computer engineering
  • Knowledge of ASIC IP design and/or verification [0 to 5 years of experience]
  • Team-oriented, prioritizing team success
  • High attention to detail and commitment to quality
  • Strong focus on meeting project deadlines and deliverables
  • Strong communication skills
Job Responsibility
Job Responsibility
  • Take part in the ASIC IP design and/or verification together with other team members
  • Develop/Improve state of the art designs [RTL] and testbenches
  • Collaborate closely with other verifiers, designers, and architects
  • Build competence in the technical domain
What we offer
What we offer
  • Competitive compensation and benefits package
  • Work-life balance
  • Continuous learning opportunities
  • Collaborative and innovative work environment
  • International work environment
  • Professional growth and career development
Read More
Arrow Right

Design Verification Engineer - SoC

We are seeking a Design Verification Engineer to join our Systems/Performance Ve...
Location
Location
United States , San Jose
Salary
Salary:
150000.00 - 275000.00 USD / Year
etched.com Logo
Etched
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • ASIC/SoC Design & Verification Experience
  • Strong understanding of digital design, RTL, and ASIC design flows
  • Hands-on experience with performance verification, simulation, and modeling
  • SystemVerilog & Python Expertise
  • Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog
  • Skilled in writing Python scripts for automation, data analysis, and performance modeling
  • Architecture & Performance Modeling Knowledge
  • Experience building and maintaining performance models for chip subsystems
  • Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators
  • Software Performance Profiling
Job Responsibility
Job Responsibility
  • Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon)
  • Work closely with software and application developers on identifying performance bottlenecks and tuning the software
  • Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification
  • Improve and maintain the architectural performance models
  • Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model
  • Develop SystemVerilog or Python-based checkers for verifying the performance features
  • Develop coverage monitors and analyze coverage to ensure all performance features are covered
  • Debug performance issues and conduct performance tuning on silicon
  • Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle
What we offer
What we offer
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Fulltime
Read More
Arrow Right

ASIC Design Engineer

Aruba is an HPE Company, and a leading provider of next-generation network acces...
Location
Location
India , Kolkata
Salary
Salary:
Not provided
https://www.hpe.com/ Logo
Hewlett Packard Enterprise
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Strong Verilog RTL coding skills
  • Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
  • Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
  • Knowledge of high performance memory subsystems
  • Knowledge of multi-domain clock synchronization and high-speed serial interfaces
  • Strong problem solving and ASIC debugging skills
  • Excellent written and verbal communications skills
  • MSEE or BSEE is required
  • 8+ years of design experience in ASIC or related fields
  • Proficiency in Verilog, VHDL, and design tools like Synopsys or Cadence
Job Responsibility
Job Responsibility
  • Define and architect high-performance blocks for the latest, most advanced networking ASICs
  • Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
  • Collaborate with the verification team in the development of the testplan and assist in debugging test failures
  • Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes
What we offer
What we offer
  • Health & Wellbeing
  • Personal & Professional Development
  • Unconditional Inclusion
Read More
Arrow Right