ASIC DDR Verification Engineer Job at AMD (Hyderabad)

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

ASIC RTL Design Engineer

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 14-18 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate, implement, and verify RTL code for complex ASICs
Own SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Lead design reviews and provide mentorship to junior engineers
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

Staff Design Verification Engineer

We are looking for an adaptive, self-motivative Design Verification (DV) enginee...

Location

Singapore , Singapore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Excellent analytical and critical thinking skills along with attention to details
Must be an initiative-taker, able to drive tasks independently and efficiently to completion
Strong/effective communication skills
Enthusiastic team-first mentality
Ability to provide mentorship and guidance to junior engineers
Proven experience in design verification from specification to successful silicon
Experience in PLL, high-speed interfaces such as DDR, PCIe and high-speed SERDES
Experience in designs with multiple power domains
Experience in designs with multiple clock domains
Experience in behavior modeling for Analog Circuits

Job Responsibility

Analyze complex verification and digital design problems and propose verification / micro-architecture solutions
Develop RTL and Firmware validation
Drive/develop ASIC verification flows and scripts
Create Verification architecture
Work with the RTL Design team to ensure functional correctness and coverage
Support silicon bring-up and diagnostics
Support Post-silicon debug, root cause bug, provide solution or workaround

Senior Engineer, ASIC Development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
4-6 years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure

Fulltime

ASIC Design Engineer

Join our innovative team in Milpitas, United States, as a Design Engineer in ASI...

Location

United States , Milpitas

Salary:

95981.00 - 135896.00 USD / Year

Sandisk

Expiration Date

May 12, 2026

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field
NCG or 1-2 years ASIC design working experience
Proficiency in Verilog/System Verilog
Proficiency in EDA tools for ASIC design and verification
Proficiency in AI tools for ASIC design

Job Responsibility

Micro architecture and RTL implementation specification, for various new IP or customize existing IP design (including but not limited to: CPU complex, DDR, Flash interface, Debug, proprietary ips)
Collaborate with cross-functional teams to ensure seamless integration of ASIC designs into larger systems
Proficiently use AI tools. Candidates must embrace emerging trends and technologies in ASIC development

What we offer

Short-Term Incentive (STI) Plan
Long-Term Incentive (LTI) program (restricted stock units or cash equivalents)
RSU awards for eligible new hires
Paid vacation time
Paid sick leave
Medical/dental/vision insurance
Life, accident and disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Other voluntary benefit programs (supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity)

Fulltime

Staff Engineer, ASIC development Engineering

As a SoC Validation/Verification Engineer, you will play a key role in ensuring ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or MS degree in Electrical Engineering or Computer Engineering
5-8+ years of experience in SoC pre-/post-silicon verification and validation, and bring-up
Deep understanding of C, embedded programming, and hardware/software co-validation methodologies
Strong knowledge of SoC verification environments, SystemVerilog (SV), and UVM concepts
Proven history of developing and executing verification and validation strategies for complex SoCs
Experience in verification and validation of industry-standard protocols such as DDR, PCIe, LPDDR, USB, Ethernet, I²C, I3C, SPI, AXI, AHB, and APB
Must understand and contribute to complex SoC-level testbenches, including UVM, C, and SystemVerilog components
Strong experience in bring-up, including board initialization, power-on sequences, processor boot, and system-level debug for both pre- and post-silicon phases
Hands-on experience in post-silicon ASIC bring-up, validation, and debug
Should have a very good understanding of C, Python, or Perl scripting languages for test automation, data analysis, and tool development

Job Responsibility

Understanding complex ASIC specifications to create comprehensive Verification/Validation plans for both pre- and post-silicon validation
Independently developing and executing tests for verification and validation
Collaborating with cross-functional teams to drive closure of verification and validation activities
Signing off on verification and validation deliverables
Debugging and root cause analysis of issues found during validation
Developing and maintaining automated test environments and regression suites
Contributing to the continuous improvement of verification methodologies and best practices
End-to-end ownership of one or more subsystems or SoC verification and validation flows, including planning, execution, and closure
Run complex SoC verification and validation scenarios on Palladium/Emulation platforms to accelerate debug and improve pre-silicon coverage
Execute verification and validation cases in simulation environments and perform initial debug and root cause analysis

Fulltime

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

Staff Engineer, ASIC Development Engineering

Are you ready to push the boundaries of what's possible in technology? Join the ...

Location

India , Bangalore

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field with 5-8 years of experience
Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Prior knowledge of Power Intent format (UPF) and Timing Constraints (SDC) is a must
Proficiency in scripting languages (e.g., Python, TCL) for automation
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Strong problem-solving skills and the ability to thrive in a dynamic environment
Excellent communication and teamwork abilities

Job Responsibility

Innovate and develop RTL code for complex ASICs
Contribute in SoC subsystems related to CPU complex, DDR, Host, Flash, Debug, Clocks, resets, Power domains etc. for top of the line flash controllers
Ensure robust design methodologies including Lint, CDC, RDC, CLP and FC-Elab
Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process
Collaborate with DFT, PD, Hardware and Firmware teams for delivering the most optimal solution
Work along side with the SoC Managers and SoC Leads to deliver best-in-class solution
Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design

Fulltime

ASIC DDR Verification Engineer

AMD

Location:
India , Hyderabad

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
April 23, 2026

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