ASIC Architect Job at Etched (San Jose)

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

ASIC Engineer Staff

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

MSEE or BSEE is required
At least 5 years of ASIC Verification Experience
ASIC Verification using SystemVerilog
Experience in constrained-random verification
Experience with verification methodology like OVM/VMM/UVM
Perl/Tcl scripting
Experience verifying networking protocols such as Ethernet
Strong problem solving and ASIC debugging skills

Job Responsibility

Provide technical expertise and lead project teams of Electronic and VLSI engineers
Review and evaluate designs for compliance with VLSI technology guidelines
Provide VLSI-specific expertise to cross-organization projects
Provide leadership to project teams of VLSI engineers
Provide guidance and mentoring to less experienced staff
Drive VLSI innovation and integration of new technologies
Architect and develop block level verification environments using System Verilog and UVM methodology
Define, architect, code, and deliver verification suites/tests for ASICs
Verify large ASIC blocks independently and sign off for tape-out
Work closely with logic designers to resolve bugs and software developers

What we offer

Health & Wellbeing benefits
Personal & Professional Development programs
Unconditional Inclusion environment
Comprehensive suite of benefits supporting physical, financial and emotional wellbeing

Fulltime

Principal Network Architect

Architect to help define the future of high-performance networking for HPC and A...

Location

United States , Ft. Collins

Salary:

142000.00 - 310500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

April 27, 2026

Requirements

Bachelor's or Master's degree in Electrical Engineering
Typically 10+ years experience
Deep understanding of network architecture and system-level design principles
Proven experience in evaluating architectural trade-offs and implementing optimization strategies
Strong ability to work effectively within cross-functional teams
Ability to effectively communicate product architectures, design proposals and negotiate options at business unit and executive levels

Job Responsibility

Define and document ASIC-level network architecture
Research and assess new networking technologies
Develop and document system-level network designs
Collaborate with network architects, ASIC designers, and software engineers to align architecture with system goals

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

New

Senior Network Performance Engineer

Senior Network Performance Engineer. This role has been designated as ‘Remote/Te...

Location

United States , Ft. Collins

Salary:

111000.00 - 243000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

April 27, 2026

Requirements

Bachelor's or Master's degree in Mechanical, Electrical, or other Engineering, Computer Science, or equivalent
Typically 6-10 years experience
Strong understanding of network architecture and system-level design
Proficiency in simulation modeling in C++ and analysis in Python
Experience in analyzing architectural trade-offs and optimization strategies
Ability to work effectively in cross-functional teams

Job Responsibility

Design and implement simulation motifs to drive realistic network scenarios
Execute performance tests on different network platforms
Validating simulation models against hardware
Create tools for performance analysis and visualization
Evaluate performance and scalability of proposed architectures
Apply software engineering best practices to ensure reliable and efficient simulation outcomes
Collaborate closely with network architects, ASIC designers, and software engineers

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

New

Senior Engineer, Firmware Engineering

In this position, the individual will be responsible for design & development of...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE/BTech/MTech degree or equivalent or higher
2+ years of experience in embedded firmware development
Excellent Embedded C programming skills
Good to have Assembly language programming skills
Must have strong problem solving skills
experience using logic and protocol analyzers is preferred
The ideal individual must have proven ability to achieve results in a fast moving, dynamic environment
Self-motivated and self-directed, however, must have demonstrated ability to work well with people
A proven desire to work as a team member across internal and cross functional teams
Ability to work effectively cross-functionally and globally

Job Responsibility

Design, implement, debug firmware for the next generation of SSDs
HW Interface drivers, algorithm design and implementation
Contribute to the SSD firmware and play a significant role in delivering next generation SSDs to market
Work with the firmware Architects, ASIC, flash media, validation and other cross functional teams on regular basis
Design and implement firmware algorithms needed to achieve best in class performance goals
Develop characterization and evaluation programs for new products
Support failure analysis on test systems
Active participation in technical design, implementation reviews across teams and functions

Fulltime

New

ASIC Engineer, Architecture

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Seattle

Salary:

198450.00 - 234520.00 USD / Year

Technologist, ASIC Development Engineering (Design Lead - High-speed IO)

Will be part of team responsible for IO and high speed interface solutions for n...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelors/Masters degree in Electronics & Telecommunication/Electrical engineering
Working experience (10+ years) in IO including 3-5 years as project leaders
Should have architected and lead high speed interface design solutions from specification through Silicon debug and characterization
Should have hands-on experience in TX and RX design architectures for high speed applications such as DDR4/DDR5/HBM/UCIe along with timing budget analysis
Should be experienced in high speed design architectures such as SERDES, Equalization schemes
Should have hands-on experience in IPs such as SSTL, LVDS, I2C, POD IOs, PVT calibration, HV tolerant and Fail-safe IOs, Crystal oscillator etc
Should have extensive experience in ESD circuits design, Associated ESD guidelines and recommendations in different process nodes, IO and SOC level ESD review and signoff
Experience in full custom high speed data path design such as DDR/HBM/UCIe PHY will be of advantage
Conversant with tools such as Cadence Virtuoso/Synopsys custom compiler/Hspice/Spectre/Finesim including statistical simulation methodologies
Experience in Mixed-mode simulation and analog/digital co-simulation will be of added advantage

Job Responsibility

Will be part of team responsible for IO and high speed interface solutions for next generation SOCs in advanced CMOS technology nodes
Will architect IO and high speed interface solutions for SanDisk ASIC controllers
Will interact with cross-functional teams to define requirements/specs, conceive the optimal solution by evaluating architectures, drive implementation, closely work with layout designers in guiding and reviewing the layouts, ensure timely and high-quality deliverables, extend SOC integration support and review and provide support for post-TapeOut activities such as Silicon characterization
Provide good technical leadership in problem solving, planning and mentoring junior engineers
Propose innovative design solutions and design methodologies
Help in building a team and developing processes

Fulltime

ASIC Engineer

Designs, analyzes, develops, modifies and evaluates VLSI components and hardware...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

3+ years of ASIC design experience
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required

Job Responsibility

Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the test plan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Architect

Etched

Location:
United States , San Jose

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 18, 2026

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