CrawlJobs Logo
Synopsis Engineering Logo Synopsis Engineering · IT - Software Development

Analog Models & Verification Engineer, Architect

United States, Chandler Employment contract 181000.00 - 271000.00 USD / Year · Job Posted January 24, 2026
Apply Position
Job Link Share

Job Description

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Responsibility

  • Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data
  • Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator)
  • Ensure models accurately capture all relevant functionalities, calibration/adaptation controls, time- and mode-dependent behaviors, key performance aspects, and residual impairments (offsets, gain mismatches, jitter, noise, skew, supply noise, etc.)
  • Interface with digital design and verification teams to guarantee exhaustive model verification—ensuring all functionalities and edge-cases are included in regression and integration test plans
  • Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation)
  • Integrate behavioral models into modern verification environments (UVM, MS-MDV), utilizing assertion-based checks, analog/digital interface scoreboards, and power-aware techniques as appropriate
  • Optimize model implementations for simulation speed and accuracy
  • Drive continuous improvement and automation in the creation, maintenance, and validation of SerDes behavioral models
  • Establish and evangelize best practices and reusable frameworks for efficient, scalable RNM modeling and mixed-signal verification
  • Mentor and support teammates, sharing knowledge, methodology innovations, and documentation

Requirements

  • BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience
  • Advanced proficiency with Verilog, SystemVerilog (including RNM, wreal modeling, and IEEE 1800-2012 SV-DC extensions)
  • Robust understanding of analog/mixed-signal SerDes sub-blocks: TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator
  • Proven ability to model analog circuit impairments: offsets, gain/mismatches, jitter, noise, skew, supply noise, etc.
  • Fluency with analog schematics, SPICE-level simulation tools and waveform analysis
  • Strong scripting/programming in Python, TCL, Perl, C/C++
  • Familiarity with verification flows: regression, analog/mixed-signal co-simulation, digital verification, gate-level simulation, formal methods, and emulation
  • Experience with UVM testbenches, assertion-driven and coverage-driven verification

What we offer

  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Annual bonus, equity, and other discretionary bonuses
Synopsis Engineering - All Job Offers

Looking for more opportunities?

Search for other job offers that match your skills and interests.

Suggested Tags: Frontend Developer Secretary Talent Manager Salesforce Administrator Data Analyst
Similar Jobs for

Analog Models & Verification Engineer, Architect

8 matching positions

Ehw Architect Engineer

Power Drive Systems: eHW Architect. Location : India Propulsion Engineering Cent...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
borgwarner.com Logo
BorgWarner
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • B.E/B. Tech/M.E/M.Tech in Power Electronics/Electronics & Communication/Electrical
  • Experience: 3 to 6 years(Grade 9)-HWA Engineer role
  • Hardware Design & development experience of ECU's of low voltage controllers
  • Experience in Analog, Digital & Power Electronics based circuit design & development for Automotive ECU's
  • Experience in HW components selection based on requirements
  • Experience in embedded microcontroller architecture
  • Experience in Serial Communication architecture
  • Knowledge of SPI, I2C, CAN, LIN communication protocol and communication bus architecture
  • Basic Knowledge in ISO26262 – Part -4 (System level) & Hardware Functional Safety Analysis (ISO26262 – Part – 5)
  • Experience in hardware requirements elicitation and validating it
Job Responsibility
Job Responsibility
  • Design & Development of ECU for LV controller
  • Specify and analyze hardware requirements and interfaces for Automotive ECU's in drive train, Engine control & transmission control areas
  • Establish bidirectional traceability, consistency check, review and baseline of the hardware requirements
  • Development of hardware architecture & hardware-software interfaces
  • ASICs configuration & collaboration with cross competency
  • Prepare hardware design document with good understanding of schematic
  • Define hardware design verification strategy and perform hardware functional testing
  • Perform Hardware troubleshooting & test report preparation
  • Fulltime
Read More
Arrow Right

Principal Quantum Design Verification Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...
Location
Location
United States , Redmond
Salary
Salary:
139900.00 - 274800.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment
  • OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • Citizenship & Citizenship Verification
  • Ability to leverage AI tools to drive innovation and efficiency
  • Ability to work in an 'AI-first' environment using modern AI tools to accelerate discovery through hardware development
Job Responsibility
Job Responsibility
  • Own verification environments and tests for IP and SoC designs, and validate designs in simulation with both pre- and post-layout Register-Transfer Level (RTL) and netlists
  • Coordinate the execution of contingent staff and external vendors to ensure verification deliverables meet specification and schedule
  • Set up and manage databases and flows for SoC and IP repositories
  • set up bug-tracking systems and log, track, manage, and close bugs and issues
  • drive milestone reviews and status reports
  • Create test plans for pre-silicon simulation verification across both digital and analog components, including the development of Analog Mixed-Signal (AMS) simulation models
  • Collaborate with the Design For Test (DFT) team to test DFT features
  • Align verification methodologies with wider teams and drive continuous improvement to Design Verification processes for at-scale execution
  • Collaborate effectively with architects, analog mixed-signal designers, verification engineers, and physical design, DFT, and other front-end design teams
  • Embody our culture and values
  • Fulltime
Read More
Arrow Right

Senior Quantum Design Verification Engineer

At Microsoft, our mission is to empower every person and every organization on t...
Location
Location
United States , Redmond
Salary
Salary:
119800.00 - 234700.00 USD / Year
https://www.microsoft.com/ Logo
Microsoft Corporation
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position
  • OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment
  • OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment
  • OR equivalent experience
  • Ability to meet Microsoft, customer and/or government security screening requirements
  • Microsoft Cloud Background Check
  • proof of citizenship or permanent residency
Job Responsibility
Job Responsibility
  • Define pre-silicon Simulation, post-silicon Validation/Characterization plans for SoC/ intellectual property (IP)
  • coordinate and drive individuals, contingent staff and external vendors towards creating a high-quality design
  • Own and create verification environments and tests for IP level and SoC level designs
  • validate designs in simulation with both pre and post layout RTL/netlists
  • Setup Databases, flows for SoC/IP repositories
  • Setup Bug-Tracking systems
  • Drive Milestone reviews, reports/status
  • Create testplans for pre-silicon simulation verification including for both digital and analog components
  • performing Analog Mixed Signal Simulation models
  • Collaborate with Design for Test (DFT) team to test DFT features
  • Fulltime
Read More
Arrow Right

Ehw architect

Location
Location
India , Bengaluru
Salary
Salary:
Not provided
borgwarner.com Logo
BorgWarner
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • B.E/B. Tech/M.E/M.Tech in Power Electronics/Electronics & Communication/Electrical
  • Experience: 2 to 4 years-HWA Engineer role
  • Hardware Design & development experience of ECU's of low voltage controllers
  • Experience in Analog, Digital & Power Electronics based circuit design & development for Automotive ECU’s
  • Experience in HW components selection based on requirements
  • Experience in embedded microcontroller architecture
  • Experience in Serial Communication architecture
  • Knowledge of SPI, I2C, CAN, LIN communication protocol and communication bus architecture
  • Basic Knowledge in ISO26262 – Part -4 (System level) & Hardware Functional Safety Analysis (ISO26262 – Part – 5)
  • Experience in hardware requirements elicitation and validating it
Job Responsibility
Job Responsibility
  • Design & Development of ECU for LV controller
  • Specify and analyze hardware requirements and interfaces for Automotive ECU's in drive train, Engine control & transmission control areas
  • Establish bidirectional traceability, consistency check, review and baseline of the hardware requirements
  • Development of hardware architecture & hardware-software interfaces
  • ASICs configuration & collaboration with cross competency
  • Prepare hardware design document with good understanding of schematic
  • Define hardware design verification strategy and perform hardware functional testing
  • Perform Hardware troubleshooting & test report preparation
  • Fulltime
Read More
Arrow Right

Principal Engineer, VLSI Design Engineering

Principal Engineer role in VLSI Design Engineering focusing on SOC Verification....
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ Years of relevant Logic Verification experience
  • Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups
  • Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
Job Responsibility
Job Responsibility
  • Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups
  • Fulltime
Read More
Arrow Right

Principal Engineer, VLSI Design Engineering

Job responsibilities: 8+ Years of relevant Logic Verification experience. Able t...
Location
Location
India , Bangalore
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 8+ Years of relevant Logic Verification experience
  • Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups
  • Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
Job Responsibility
Job Responsibility
  • Able to lead and Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups
  • Fulltime
Read More
Arrow Right

Staff Engineer, VLSI Design Engineering

Develop test plans, tests and verification infrastructure for a complex IP/Sub-S...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5 to 7 years of relevant experience
  • B.E/B.Tech/M.Tech in ECE/VLSI/Electrical Engineering
  • Proficiency in Computer Science fundamentals – object oriented design, data structures, algorithms, design, problem solving, and complexity analysis
  • Basic knowledge of with c, c++, SystemC, perl, python, tcl, shell is preferable
  • Unit/Sub-system/SOC level verification experience
  • Experience in leading verification closure of complex IP/SOC for at least one project
  • Exposure to industry standard verification tools for simulation and debug
  • RTL & Gate Level Simulations
  • Proficiency in Verilog, System Verilog, Assertions and UVM
  • Exposure to Verification Fundamentals
Job Responsibility
Job Responsibility
  • Develop test plans, tests and verification infrastructure for a complex IP/Sub-System or lead major deliverables for SoC
  • Create verification environment using UVM methodology
  • Hands on in end to end Logic Verification Process including Verification Planning, Functional Coverage planning and development, Test case development, regression, debug and Coverage closure
  • Create reusable bus functional models, monitors, checkers and scoreboards
  • Drive functional coverage driven verification closure
  • Work with architects, designers, and post-silicon teams
  • Hands-on contributions to SVA development like coding, porting and maintaining System Verilog Assertions including Formal Verification
  • Development of tools for Design and Verification support
  • Debug failures and root-cause it by interacting with other teams/groups
  • Fulltime
Read More
Arrow Right

Analog/Mixed-Signal IC Design Director

SCALINX is seeking a highly influential Analog/Mixed-Signal IC design team leade...
Location
Location
France , Paris/Caen/Grenoble
Salary
Salary:
Not provided
scalinx.com Logo
SCALINX
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Proven industrial experience in: Architecture/design & validation of high-speed Nyquist-Rate data converters IP blocks (time-interleaved pipeline/SAR ADC architecture & current-steering DAC architectures)
  • Architecture/design of calibration circuits enhancing data converters performance
  • Integration of high-speed data converters IP blocks in complex mostly digital SoC (with strong knowledge of mixed-signals verification strategies/tools, signal integrity/power integrity & crosstalk issues)
  • Strong understanding of clocking circuit concepts and design trade-off to implement high-performance, high-speed data converters
  • Expert in AMS design/layout methodology
  • Experience in supervising mixed-signals designers and able to dive into technical details (down to transistor level)
  • Work across teams: Strong ability to resolve complex cross-functional issues
  • Design experience in advanced CMOS process
  • Excellent verbal and written communication (English required)
  • 15+ years of experience in IC design and technical leadership
Job Responsibility
Job Responsibility
  • Manage a team of ~25 people including architects and AMS design/layout engineers in the field of deep sub-micron technology SoCs
  • Lead all aspects of design from concept to production, including architecture, specifications, transistor-level design, modelling, verification, layout, post-silicon validation support, productization support, etc.
  • Lead cross-functionally to ensure program cohesion with teams such as marketing, systems design, digital front-end/back-end teams, validation, productization, quality, applications, packaging, etc.
  • Ensure quality and reliability standards are met for volume production
  • Develop methodology and processes for “first time right” products
  • Participate in communication with high-profile customers
  • Actively participate in the technology roadmap definition
  • Report development progress to executive management
  • Fulltime
Read More
Arrow Right