Analog Layout Engineer Job at AMD (Bangalore)

Analog Layout Engineer

At AMD, our mission is to build great products that accelerate next-generation c...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Engineering in electronics is desired
Masters in electronics is preferred
Any certification course(s) in VLSI custom layout field will be an added advantage
Custom layout expertise in lower technology
Digital, Analog and mixed signal layout
Good understanding of reliability concepts
Good understating of layout electrical parameters and closure

Job Responsibility

Candidate should be able to handle sub cells/leaf cells that are needed to build IP/macro using CAD tools
Chip level integration, physical verification and electricals’ closure
Over time candidate will be exposed/experienced to various other fields of custom layout
candidate should own a complex design block

Senior Quantum Analog Layout Engineer

Microsoft's Quantum team is building the first scalable, fault-tolerant quantum ...

Location

United States , Redmond

Salary:

119800.00 - 234700.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 1+ year(s) experience in industry or in a research and development environment, could include completion of a post doctoral research position OR Master's Degree in Physics, Engineering, or related field AND 4+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role, including the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status for assessment of eligibility to access the export-controlled information
Ability to leverage AI tools to drive innovation and efficiency
Ability to work in an AI-first environment using modern AI tools to accelerate discovery through hardware development.

Job Responsibility

Deliver Schematic-to-Graphic Database System (GDS) layouts for cutting-edge, high-performance, high-speed, low-power IP designs, including interconnectivity solutions and foundational Analog circuit blocks
Execute these layouts across multiple process nodes, including deep Fin Field-Effect Transistor (FinFET), following industry best practices
Develop plans for Analog Mask Layout execution and follow processes and methodologies to deliver IP blocks
Coordinate tasks with junior layout team members as needed
Using Cadence Virtuoso (or other equivalent) design tools and flows
perform layout implementation of analog-intensive IPs and help establish flows, methodologies, and processes for execution alongside peers
Support the on-boarding and off-boarding of contingent layout staff and vendor partners as needed
help direct their day-to-day execution to ensure quality and schedule are met
Work with other members of the team to deliver IPs, including project planning, schedule tracking, and report generation
Follow, augment, or put in place processes and methodologies for high-quality execution alongside peers

What we offer

Certain roles may be eligible for benefits and other compensation
Find additional benefits and pay information here: https://careers.microsoft.com/us/en/us-corporate-pay

Fulltime

Staff Analog Layout Design Engineer

The focus of this role is to plan, build, and execute the verification of new an...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Proficient in IP level ASIC verification
Proficient in debugging firmware and RTL code using simulation tools
Proficient in using UVM testbenches and working in Linux and Windows environments
Experienced with Verilog, System Verilog, C, and C++
Graphics pipeline knowledge
Developing UVM based verification frameworks and testbenches, processes and flows
Automating workflows in a distributed compute environment
Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
Strong background in the C++ language, preferably on Linux with exposure to Windows platform
Good understanding and hands-on experience in the UVM concepts and SystemVerilog language

Job Responsibility

Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
Estimate the time required to write the new feature tests and any required changes to the test environment
Build the directed and random verification tests
Debug test failures to determine the root cause
work with RTL and firmware engineers to resolve design defects and correct any test issues
Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements

Fulltime

Senior Analog Layout Design Engineer

AMD is looking for a candidate to design the layout for digital and analog circu...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Must have detailed knowledge of CMOS circuit theory
Must have ability to communicate with various teams to articulate specs and requirements as they pertain to layout
Layout design and verification experience using Cadence Virtuoso and Mentor Calibre tools
Must have at least 5 years of relevant or comparable experience doing analog layout design
Experience in LVS, DRC, ERC, ANT, ESD, Latch-up, EMIR and Reliability
Good understanding of signal and clock shielding and isolation techniques
Ability to work well as part of a team
Bachelor's degree in Engineering (or related field) OR Associates Degree in Engineering.

Job Responsibility

Layout of basic digital and analog building blocks using analog transistor level components
Layout of analog macros, power pads, and input/output pads using above blocks
Working closely with Analog designers in floorplanning
power grid and signal flow planning
Physical and electrical verification include DRC, LVS, EM/IR, ERC, PERC Latch up and PERC ESD
Creation of blackbox models for other groups in the design flow

Fulltime

Mixed Signal Custom Layout Engineer (1-Year Temporary)

The full custom IC layout group is looking for a candidate to design the layout ...

Location

Canada , Markham

Salary:

86400.00 - 129600.00 CAD / Year

AMD

Expiration Date

Until further notice

Requirements

Strong understanding of CMOS device/circuit theory and analog/digital layout best practices
Custom layout using Cadence Virtuoso
Physical verification using Mentor/Siemens Calibre (LVS, DRC, PERC) and ERC/EM/IR flows
Scripting/automation in Perl, TCL, SVRF/TVF, SKILL is a plus
Exposure to advanced nodes (e.g., 2nm/3nm
experience at 5nm/7nm also valued)
Background with IP/standard-cell layout, high-speed differential signaling, PLL/DLL/VCO, DACs, power pads, and in-context XOR
Electrical/Mechanical Engineering Degree and/or Electronics related Diploma

Job Responsibility

Create clean, robust layouts for digital and analog building blocks at the transistor level in Cadence Virtuoso
Floorplan, route, and assemble lower-level cells into macros
Build black-box/abstract models and views consumed by other teams
contribute to tapeout collateral for custom blocks
Run hierarchical checks at cell/macro levels (DRC, LVS, ERC, EM/IR, Latch-up/ESD) and iterate to closure in partnership with circuit owners
Explore and leverage AI-assisted tools and workflows to improve layout productivity, verification efficiency, and design quality

Fulltime

New

Principal Analog & CAD Engineer

At Microsoft Quantum, we aim to empower science and scientists to solve the worl...

Location

United States , Redmond

Salary:

142800.00 - 304200.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Physics, Engineering, or related field AND 3+ years experience in industry or in a research and development environment OR Master's Degree in Physics, Engineering, or related field AND 6+ years experience in industry or in a research and development environment OR Bachelor's Degree in Physics, Engineering, or related field AND 8+ years experience in industry or in a research and development environment OR equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role
Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR), the EU Dual Use Regulation, and/or other export control regulations
Ability to leverage AI tools to drive innovation and efficiency (e.g., performance modeling and analysis, research gathering, day to day task automation)
Ability to work in an “AI-first” environment using modern AI tools to accelerate discovery through hardware development

Job Responsibility

Responsible for auditing external foundries to find a suitable partner for long-term engagement for Microsoft quantum/cryo silicon programs
Evaluate their solutions for materials/process tailoring to match our needs
Create long-term evolution plans with vendors for evolving process needs for future quantum products
Responsible for finding / defining design development libraries and re-characterizations for standard cells and analog design PDKs at cryo temperatures
Responsible for setting CAD Tool flows for our ASICs in collaboration with a centralized CAD Infra tools team
Responsible for Analog Design of cryo-CMOS components
Responsible for Quantum/Cryo-CMOS layout solution path-finding

Fulltime

Senior Analog Design Engineer

We are the global test and automation specialists, powering next-generation tech...

Location

United States , Agoura Hills

Salary:

123100.00 - 193900.00 USD / Year

Teradyne

Expiration Date

Until further notice

Requirements

MSEE with 5 years of experience or PhD in electrical engineering with 3 years experience in the design and characterization of multiple, high frequency and high scale of integration mixed signal integrated circuits
Thorough knowledge of high frequency, broad-band Analog Mixed-Signal IC design – both electrical and physical design
Desire experience in design of VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high frequency I/Os, high frequency CML designs, high voltage, power circuits
Solid understanding of CMOS semiconductor device physics and device modeling
Solid understanding of electromagnetic theory
Solid understanding of transmission line theory
Solid understanding of thermal effects of various circuit topologies and different package types
Involvement in all phases of multiple IC developments from specification to product introduction
Solid understanding and experience with IC characterization at high frequencies using high speed sampling oscilloscopes, spectrum analyzers, VNAs, signal sources
Solid understanding of working with PDKs

Job Responsibility

Develop detailed circuit specifications for mixed signal circuits
Conceive circuit architectures and transistor level circuit topologies that satisfy required performance
Physical implementation (layout) of high speed circuits, either directly or assisting
Optimization of circuits via simulation (with Cadence EDA tools) over all process and operating conditions
Integration of circuit elements into large analog/mixed signals ASICs
Participation in the characterization of ASIC circuits

What we offer

medical
dental
vision
Flexible Spending Accounts
retirement savings plans
life and disability insurance
paid vacation & holidays
tuition assistance programs

Fulltime

Analog Design Engineer

This job opening is for a circuit designer in a team responsible for high-precis...

Location

India , Bangalore

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

Masters in Electrical/Electronics Engineering, with specialization in microelectronics or something similar
Strong hands-on experience in SerDes and/or DDR circuit designs in latest technology nodes, including Finfet
Good technical knowledge of power-performance trade-offs in high-speed SerDes designs
Direct experience in all phases of design analysis including functional, static timing and electrical sign-off
Strong understanding of the impact of variation on design performance
Strong circuit design knowledge
Clear communication and presentation skills
Diligent documentation of work

Job Responsibility

Complete ownership of individual circuit blocks in a SerDes PHY design in cutting edge FinFet technology nodes
Responsible for circuit design, layout quality, electrical and timing analysis, and reliability checks
Interface with cross-functional teams like RTL, Verification and Physical Design

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Analog Layout Engineer

Job Description

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